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Modelsimhelp
- Modelsim 5.6 se 简易使用教程
naozhongsheji
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 闹钟设计-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Alarm Clock Design
honhludeng
- 软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 用VHDL语言仿真交通灯-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Using VHDL language simulation of traffic lights
TestBench
- 怎样写testbench 本文的实际编程环境:ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_log
CPU
- verilog 实现的CPU,用Modelsim SE 6.2b 创建的工程,包含测试文件。- CPU of verilog implementation
modelsimPcrack
- modelsim 的crack,能够破解6.5se-modelsim of the crack, to break 6.5se
Crack_ModelSim_SE_6.3d
- Modsim6.3 Crack and license
Modelsim_6.5_SE
- Modelsim_6.5_SE的安装方法,描述的非常详细,十分轻松的安装好!-Modelsim_6.5_SE installation method, described in great detail, very easy to install!
adfmreceiver
- The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia p
Principles-of-computer-
- 用verilog语言描述 计算机的30条指令的实现 然后再ModelSim SE 6.1f下仿真-Verilog language descr iption of the computer 30 instruction under the simulation and then ModelSim SE 6.1f
or1200_sopc
- 用verilog语言编写的or1200+wishbone总线+串口uart+片上ram,最小系统soc。包括片上ram的软件系统(C语言编写)都有。但下载者要使用此系统需要很多工具链,搞soc的应该都装好了。 绝对原创!用quartusII11.0在Altera DE2-115上验证通过,Modelsim SE 6.5f仿真通过。-It s very strange for Chinese people communicating with each other in English. Ri
Chapter2
- Chapter2文件夹:(1)Quartus II 8.0软件实例讲解:1位加法器实验,完整的设计工程文件在Chapter2/adder文件夹下(2)ModelSim SE 6.0软件实例讲解:十进制计数器实验,完整的设计工程文件在Chapter2/test_counter_10文件夹下 -Chapter2 folder: (1) the Quartus II 8.0 software examples to explain: an adder experiment, a complete
RS232
- (6)实验6:串口通讯实验,完整的设计工程文件在RS232文件夹下二、运行环境 程序在以下环境调试通过: (1)Windows XP; (2)Altera公司的Quartus II 8.0 for windows; (3)Altera公司的Nios II 8.0 IDE for windows; (4)Mentor公司的ModelSim SE 6.0;-(6) (2) Altera Corporation Quartus II 8.0 for windows Exp
modelsim-SE-PLUS-6.5
- 自己总结的关于modelsim6.5的一些用法,希望可以与大家分享-something on the use of modelsim 6.5
I2C_EEPROM
- 1. 本测试是夏宇闻 verilog数字系统设计教程,中的例程。 2. 编译环境Quartusii 3. 仿真环境Modelsim se 6.5d 4. 可综合部分已经经过quartus 验证正确 5. 仿真部分通过将I2C模块与一个EEPROM模型组合,通过时序仿真-EEPROM_I2C Verilog
FPGA_ENVIRONMENT_BUILD
- FPGA环境的搭建,安装altera qaurtus ii 11.1和modelsim 6.5d se 图形化简单实用。-FPGA environment to build, install altera qaurtus ii 11.1 and modelsim 6.5d se graphically simple and practical.