搜索资源列表
add.rar
- 流水线乘法器与加法器 开发环境:Modelsim(verilog hdl),Multiplier and adder pipeline development environment: Modelsim (verilog hdl)
ALU.zip
- VHDL实现cpu核心逻辑与运算单元模块的实现,完成4bit*4bit输入8bit输出的运算,可做加减乘除逻辑移位6种操作,the implementation of Arithmetic and logic unit based on VHDL, can do as the adder,subtractor,multiplier,divider,shifter and logic operation.
qfq.rar
- 移位相加乘法器设计。附有工程实例及ppt说明。,Add multiplier design shift. Ppt with example and descr iption.
shilianGraphic.rar
- 主要功能 : 1、画图,并有坐标尺 2、能够随意的放大缩小(编写两个函数,分别对应X,Y粥的缩放倍数) 3、一个记录集(或链表),记录当前画了多少图形,分别是什么图形,颜色,状态等 4、一个枚举类型,枚举所有本控件能画的图形(长方形,正方形,三角形 及自定义(即鼠标随意画)等) 5、能通过鼠标删除所画图形,并能移动图形,填充图形等 6、能够导出位图文件(bmp)
cheng1.rar
- 用VHDL实现十六位移位乘法器 才有移位相加法来实现,Use VHDL to achieve 16-bit shift multiplier shift only the sum of law to achieve
RTL
- 256位有符号整数乘法器,个人学习时编写,接口为IPBUS,用verilog语言编写-256-bit signed integer multiplier, when writing individual learning, the interface IPBUS, with verilog language
Adaptive-digital-filter
- 自适应数字滤波器中乘法器的硬件设计,用VHDL语言实现自适应数字滤波器。-Adaptive digital filter in multiplier hardware design, using VHDL language adaptive digital filter.
multi8x8
- 该源码为8位乘法器的VHDL语言描述,由一个8位右移寄存器,2个4位加法器例化成8位加法器,一个16位数据锁存器构成。采用移位相加的方式,从被乘数的低位开始,与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit add
MSP430
- MSP430头文件详解,介绍特殊功能寄存器地址和控制位,看门狗定时器的寄存器定义, 硬件乘法器的寄存器定义。-Detailed MSP430 header files, describes the special function registers the address and control bits, the watchdog timer register definitions, hardware multiplier register definitions.
AD633-spice
- 模拟乘法器的PSPICE模型,可用于Multisim仿真等-PSPICE model of analog multiplier can be used Multisim simulation, etc.
mul64
- Verilog实现的64位乘法器,该乘法器是我所见过的最牛的乘法器、运算快、资源利用少-Verilog implementation of the 64-bit multiplier, the multiplier is the most I have ever seen cattle multiplier, computing faster, less resource utilization
snort-1.0
- snort1.0的代码,学习snort的好东西,现在snort很庞大,不易理解,但是1.0的代码包含了最基本的功能,读者可以在看完1.0的代码后再去理解现在snort的一些功能相信会有事半功倍的效果-snort1.0 code, learn the good things snort, snort now very large and difficult to understand, but the 1.0 code that contains the most basic functions,
twice_freqencey
- 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
FushuTest
- 用来实现两个复数的加减乘数 输出形式是实部,虚部分开 -Is used to achieve the addition and subtraction of two complex multiplier output form the real part, imaginary part of the open-
Booth_mult
- Booth multiplier for multiplication of 2 bit binary nos.
shiyan3niu
- 1.利用FLEX10KE系列(EPM10K100EQC240-1X)的CLOCKBOOST (symbol:CLKLOCK),设计一个2倍频器,再将该倍频器2分频后输出。 对其进行时序仿真。 2.设计一个数据宽度8bit,深度是16的 同步FIFO(读写用同一时钟),具有EMPTY、FULL输出标志。 要求FIFO的读写时钟频率为20MHz, 将1-16连续写入FIFO,写满后再将其读出来(读空为止)。 仿真上述逻辑的时序,将仿真
mult8_csdn
- 用verilog语言编写的8位乘法器,完成了8位二进制的整数乘法,供大家参考-Verilog language with 8-bit multiplier, completed the 8-bit binary integer multiplication, for your reference
H264
- H264编解码的流程图,非常实用,一边写程序,一边查询流程.事半功倍-H264 encoding and decoding of the diagram, very practical, while writing programs, while the query process. Multiplier
YCbCr_RGB_10bit
- YCbCr 转 RGB模块,以应用于项目中。 该模块可将10bitYCbCr分量视频转换为12bitRGB视频,需消耗乘法器。-YCbCr turn RGB module, to apply to the project. The module can be 10bitYCbCr component video converted to 12bitRGB video, need to consume multiplier.
exact_alm_rpca
- RPCA (Robust Principal Component Analysis)是目前用于矩阵填充、图像去噪的最有效的优化方法。该代码是求解RPCA的一种数值算法——Exact ALM(Exact Augmented Lagrange Multiplier)-The most basic form of the exact ALM function is [A, E] = exact_alm_rpca(D, λ), and that of the inexact ALM function i