搜索资源列表
MULT
- 乘法器 verilog CPLD EPM1270 源代码-Multiplier verilog CPLDEPM1270 source code
LSD-TEST430F5438-01_V1.1StudyBoardInstructor
- 利尔达MSP430F5438学习板的中文资料,包含硬件链接,以及IO、UCS、FLASH、WDT、TimeA、TimeB、DMA、硬件乘法器、RTC、RAM、ADC12、UART、SPI、I2C、CRC等各种操作的试验代码。-利尔达board MSP430F5438 learning Chinese data, including hardware, links, and IO, UCS, FLASH, WDT, TimeA, TimeB, DMA, hardware multiplier, R
AB4F
- FPGA编码器4倍频VHDL程序 对初学FPGA有帮助。-FPGA Encoder 4 multiplier VHDL program to FPGA beginner help.
VHDL语言写的简易计算器
- 用VHDL写的简易计算器，包括加减乘除，除法器用加法器和乘法器组成-Write simple calculator with VHDL, division, including add, subtract, multiply and divide adder on time-multiplier and used
mul
- 八位乘法器的VHDL程序，按照乘法的运算规则利用分支语句判断所有情况，最后累加求的结果-8 multiplier VHDL programs, in accordance with rules of multiplication operations to determine all the circumstances of the use of a branch statement, the final cumulative result of demand
multiplyingunit
- 其乘法器原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位-Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the l
mult16s
- 16位乘法器，VHDL语言编写的，供大学交流学习-16-bit multiplier
8-bit
- 最基本的vhdl運算，採用8bit作乘法器，將兩串8bit的值輸入之後進行相乘-VHDL basic computing, the use of 8bit for the multiplier, will be the value of two strings of 8bit input multiplied after
GFverilog-hdl
- 伽罗华域的乘法器的设计，使用有限域设计乘法器-Galois field multiplier design, the use of finite field multiplier design
fft
- 基于VHDL语言编写的FFT程序，256点，旋转因子存在自己编写的ROM里面，乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
bei
- 应用VHDL语言写的倍频器，通过对高频信号的分频得到较低频率信号的倍频-Applications written in VHDL multiplier, high-frequency signals through low frequency signal divided by the frequency
add_tree_mult
- 8位加法树乘法器,实现两个8位二进制数相乘，采用verilog hdl-8-bit adder tree multiplier, the achievement of the two 8-bit binary number multiplied, using verilog hdl
Hardware_Multiplier
- 用VHDL写的硬件乘法器，以及测试过了，一个时钟周期内完成乘法运算。被乘数、乘数的宽度通过通用属性GENERIC参数改变而轻松改变，硬件除法器也快好了。-Written by VHDL hardware multiplier, and tested, and a clock cycle multiplication. Multiplicand, multiplier width parameter changes through the common property of GENERIC an
multiper
- 用xilinx写的vhdl乘法器。是二进制的两位乘法器。里面含有代码和电路图。-Written in VHDL using Xilinx multiplier. Binary multiplier is two. Which contains code and circuit diagrams.
fisher
- 基于Fisher准则线性分类器设计，理解Fisher准则方法确定最佳线性分界面方法的原理，以及Lagrande乘子求解的原理。-Based on Fisher linear classifier design guidelines, understanding the criteria Fisher method to determine the best linear method of the principle of the interface, as well as solving La
fq_div
- pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
mult16
- 基于wallance树的16位乘法器，程序是用verilog写的，经测试好用，对初学者有很大的帮助-16-bit multiplier, based on wallance tree program is written with verilog test handy for beginners great help
pll(FPGA)
- 利用VHDL语言对FPGA进行锁相环倍频，经调试已经在开发板上实现倍频-The FPGA using VHDL language PLL frequency multiplier, the debug board has been achieved in the development of frequency
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
mul
- 定点乘法器的FPGA仿真，对于学习硬件设计的朋友应该有帮助-Fixed-point multiplier FPGA simulation, hardware design for the study should help a friend