搜索资源列表
WISHBONE-Interconnect-Matrix-IP-CORE
- 来自opencores.org 开源IP 很好的资料，供大家学习-WISHBONE Interconnect Matrix IP CORE
i2c_latest.tar
- i2C总线的控制器核，实现了I2C的主站功能。-I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol
or1200_ep3c16_board
- OpenRisc是OpenCores组织提供的基于GPL协议的开放源代码的RISC（精简指令集计算机）处理器。有人认为其性能介于ARM7和ARM9之间，适合一般的嵌入式系统使用。最重要的一点是OpenCores组织提供了大量的开放源代码IP核供研究人员使用，因此对于一般的开发单位具有很大的吸引力。-OpenRisc is based organizations OpenCores the GPL open source RISC (Reduced Instruction Set Computer
ethoc
- OpenCores Ethernet MAC driver for Linux v2.13.6.
i2c-ocores
- I2C bus driver for OpenCores I2C controller for Linux v2.13.6.
spi-oc-tiny
- OpenCores tiny SPI master driver for Linux v2.13.6.
opencores-or1k-pic
- Aic94xx SAS SATA driver register access.
modbus_latest.tar
- modbus的fpga实现。opencores上最新版本。使用fpga实现，可以大大提高响应速度，对其功能进行模块化。-modbus of fpga implementation. opencores the latest version. Use fpga implementation, can greatly improve the response speed, its function modularity.
vga_lcd_latest.tar
- 该OpenCores的增强VGA/ LCD 控制器核心提供了VGA 能力的嵌入式系统。它 同时支持CRT和LCD显示器 与用户可编程的分辨率 和视频定时，从而提供了 几乎所有可用的兼容性 LCD和CRT显示器。-The OpenCores Enhanced VGA/LCD Controller Core provides VGA capabilities for embedded systems. It supports both CRT and LCD
ocfb
- OpenCores VGA LCD 2.0 core frame buffer driver.
spi-oc-tiny
- OpenCores tiny SPI master driver.
spi_oc_tiny
- struct tiny_spi_platform_data - platform data of the OpenCores tiny SPI.
H264.opencores
- h.264解码器源码,包含所有文件，可成功仿真，贡献给大家-H.264 decoder
wb_uart_latest.tar
- 实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。 请找到有关于UART内核的文档。 该接口是现在有8位Wishbone总线兼容。 随着GHDL模拟器只需运行： ./ghdl_uart.bat 使用任何其他模拟器，开始模拟以下perl脚本必须运行之前： uart_test_stim.pl> FILENAME.TXT 其中，FILENAME.TXT是通用的“stim_
I2c_opencores_v13.0
- i2c opencores module for Altera Avalon bus. Verilog.
turbocodes_latest.tar
- 基于sova算法的Turbo码解码VHDL工程文件，非常经典，包含Python高层仿真代码。-Turbo Decoder Release 0.3 MAIN FEATURES - * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizabl
JTAG_Example0_Verilog
- 一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
pipelined_fft_64_latest.tar
- 64点混合基fft，具体时序需要小的修改就可以用了 在Opencores上面找到的 初学者可以看看(64 point mixed base FFT, the specific timing requires minor modifications can be used Found in Opencores above beginners, you can see)
ha1588-master
- ieee1588时钟同步开源，opencores上找到的，希望对大家的学习有帮助。(Ieee1588 clock synchronization open source, found on opencores, hope to help everyone's learning.)
gcc-3.4.4.tar.bz2
- The OpenCores OpenRISC 1000 Simulator and Tool Chain