搜索资源列表
MIPSCPU_MultiCircle
- 流水线的一个循环源码设计,基于mips流水线的设计-Pipeline a loop source design, based on the design of the mips pipeline
MIPSCPU_Pipeline
- 流水线的设计,基于mips流水线的管道设计-Pipeline design, pipeline design based on mips pipeline
pipelined_mmmips
- pipeline implementation of simple mips in computer architecture with hazards included.
CHU92A
- MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA
s_mips
- FPGA verilog mips processor - pipeline reference
PipelineCPU
- 这是我们设计的一个MIPS流水线CPU,基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于,5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型,这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句,从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU
MIPS789
- 一个32位的5 级流水线处理器。在构架这个处理器的结构过程中是按照MIPS指令进行各个流水段的功能划分,并且在处理各种相关的时候参照了手头上的一个GCC_MIPS的C 语言编译器,因此支持MIPS 1指令系统。编译器的支持使这个核心有了实用价值,这个核心可以应用于各种嵌入式系统设计,代替常规的单片机实现片上系统,还可以在一个芯片里加入多个内核并且灵活的总线连接实现多处理器设计。-A 32-bit pipelined processor 5. In the framework of this pr
PipelineCPU
- 设计一个32位流水线MIPS微处理器,具体要求如下: 1. 至少运行下列MIPS32指令。 ①算术运算指令:ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 ②逻辑运算指令:AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 ③移位指令:SLL、SLLV、SRL、SRLV、SRA。 ④条件分支指令:BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。 ⑤无条件跳转指令:J、JR。 ⑥数据传送指令:LW、SW
p21
- mips pipeline的源代码,很简洁,很适合新手使用。大学三年级的必修课。-mips pipeline source code, very simple, very suitable for beginners to use. University of grade three compulsory.
MIPS32
- 此資料夾為實現一單一時脈週期MIPS32處理器架構源碼,包含了控制單元、資料記憶體、資料路徑、指令記憶體四個部分,以程式碼: (共10個) instruction_mem.v、data_mem.v control.v、alu_control.v program_counter.v、reg_file.v alu_32bit.v、adder_32.v、sign_extend.v來實現。-MIPS (originally
cpu_design
- FPGA MIPS架构CPU,五段流水线功能,ISE开发,verilog语言,可综合,模拟结果正确,内含设计报告-FPGA MIPS CPU, simple five-stage pipeline function, developed by ISE, using verilog language
Elham-Zahraei-Salehi_-Sina-Saharkhiz-(1)
- here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily
ppv2
- pipeline流水线用MIPS实现,用的是verilog。解决流水线的各种冲突。-pipeline pipeline with MIPS implementation, using verilog. Resolve conflicts pipeline.
Pipeline5
- Introduction to design MIPS-pipeline processor
h.Mohseni_pipe_line
- mips processor 5 stage pipeline
MIPS_SC_v0
- Exercise MIPS (Microprocessor without Interlocked Pipeline Stages) in linguagem C-Exercise MIPS (Microprocessor without Interlocked Pipeline Stages) in linguagem C++
fgber_functional
- mips pipeline 模以程序,mfc实现的,功能就不用说了把,大家都知道的,-MIPS pipeline mode to process, MFC implementation, functions are needless to say, we all know,
bmacu_solution
- mips pipeline 模以程序,mfc实现的,功能就不用说了把,大家都知道的,-MIPS pipeline mode to process, MFC implementation, functions are needless to say, we all know,
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU,含代码工程文件和相关设计说明文档,比较详细。-verilog HDL, 32 MIPS pipeline CPU
zvltipls-vector-hyperlink
- mips pipeline 模以程序,mfc实现的,功能就不用说了把,大家都知道的,-MIPS pipeline mode to process, MFC implementation, functions are needless to say, we all know,