搜索资源列表
pll
- 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
dds
- 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
DPLL
- 数字锁相环频率合成器的vhdl实现的源代码-Digital PLL Frequency Synthesizer vhdl source code to achieve
fq_div
- pll 的64倍频 锁相环技术用 实现倍频 从而达到对频率的分频-pll 64 multiplier PLL multiplier used to achieve so as to achieve the sub-band of frequencies
FPGAPLL
- FPGA做的PLL 可以使用，比软件自带的省一些资源-PLL can be used FPGA to do more than the software comes with some of the resources of the province,
singnal
- VHDL实现通用通信信号源，包括sin，cos，方波，三角波，BPSK，GMSK，ASK，16QAM等信号的产生以及DDS，PLL的VHDL系统代码-VHDL implementation of universal communication sources, including sin, cos, square, triangle, BPSK, GMSK, ASK, 16QAM and other signal generation and DDS, PLL system, the VHDL
DE2_VGA3
- The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow
006
- 基于FPGA实现的一种新型数字锁相环-Based on the FPGA realization of a new digital PLL
shuzisuoxiang
- 数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用。与传统的模拟电路实现的PLL相比，DPLL具有精度高、不受温度和电压影响、环路带宽和中心频率编程可调、易于构建高阶锁相环等优点。-Digital phase-locked loop (DPLL) technology in digital communications, radio electronics, and many other fields has been extremely wide range of
ad_pll
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
clock
- 由锁相环(PLL)产生所需的2分频与4分频时钟8分频时钟 clk.qpf为可执行主程序 -By the phase-locked loop (PLL) have the necessary 2-and 4-frequency clock frequency of 8 minutes for Executable clk.qpf main clock
dds9851
- 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct
DPLL
- pll 的数字实现大家 支持 第一次 传-pll digital impliment
pll
- 实现了pll功能，有利于初学者学习pll，采用文本编辑的，利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design
VCO_WITH_PLL
- Voltage controlled oscillator with p-Voltage controlled oscillator with pll
altpllpll
- 用VHDL语言编写的锁相环源代码，可用于配置FPGA，在FPGA中实现ＰＬＬ功能。-VHDL language with PLL source code, can be used to configure the FPGA, PLL function is implemented in the FPGA.
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
lmk04800 family controller
- VHDL code to configure lmk04800 family pll chips, that is well tested in 7-series FPGAs.
4_pll_test
- 基于Xilinx的Artix7实现PLL。(Implementation of PLL based on Artix7)