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11223344scan_led1000
- Quartus环境下的1000进制计数器的扫描显示电路-Quartus environment under the 1000 counter-band scanning display circuit
23565785scan_led
- Quartus环境下的7段扫描显示电路的源程序-Quartus environment of the seven scanning display circuit of the source
55478362cntshow
- Quartus环境下的12进制计数器的扫描显示电路-Quartus environment of the 12 counter-band scanning display circuit
123424475SINGT
- Quartus环境下的正选信号发生器的实验源码-Quartus environment is the election of signal generator FOSS
234352325DECL7S
- Quartus环境下的7段译码管的扫描显示电路-Quartus environment of the seven decoding of the scan show circuit
ddsquartus
- 使用QUARTUS 2编译的DDS的源码-QUARTUS use two compiled the DDS source
ASYfifo
- 这是FIFO程序，开发工具是ISE或QUartus。-procedures, development tools or QUartus ISE.
fir_finall
- 用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
verilog50%
- 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the
jicifenpinqi
- 别人编写的奇次分频器，用VHDL写的，我已经在QUARTUS上验证过了-others prepared by the odd dividers, VHDL write, I have QUARTUS tested the
nios_uart
- 基于Nios II的串口通信，在quartus的开发环境中进行的实验-based Nios II Serial Communication in quartus development environment for the conduct of the experiment
38encode
- 三八译码器的源代码，在quartus II 6.0中进行进行设计的，有vhdl源代码-March 8 decoder source code, in quartus II 6.0 for the design, Source code is vhdl
SVGA_quartus
- 在开发板上实现svga条形信号发生器的源代码，是在quartus II 6.0的开发环境中运行的-achieved in the development of board svga strip signal generator source code, in quartus II 6.0 development environment running on
656to601
- 本程序实现视频图象的CCIR656转换CCIR601格式,使用的环境是Quartus II 4.0-the program CCIR656 video image conversion CCIR601 format, The environment is the use of Quartus II 4.0
lcd4quartus
- 128×64单色点阵LCD的quartus工程文件-128 x 64 monochrome dot-matrix LCD quartus works documents
3des-VHDL
- 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus
AlteraQuartusII6.0crack
- Altera Quartus II 6.0 破解文件-Altera Quartus II 6.0 crack documents
fcout
- 频率计源代码，性能很好，verilog写的，顶层原理图，底层语言写的，效果很好，开发环境为quartus-Cymometer source code, good performance, verilog written by the top diagram, the bottom language was written. good effect, and development environment for quartus
2FSK2psk
- ２ＦＳＫ２ＰＳＫ－二进制频移键控和相移键控信号发生器的源程序，是基于ＱＵＡＲＴＵＳ ＩＩ软件平台，使用ＶＨＤＬ语言-2FSK2PSK-binary frequency shift keying and phase shift keying signal generator source, QUARTUS II is based on the software platform, the use of VHDL
q2_7_license
- altera quartus 2 7.0 许可文件-altera quartus 2 7.0 permit documents