搜索资源列表
DDS_GEN
- Functional Generator in DDS AD9953 (AD9954) Freq.: 1Hz....30MHz Out.: 2mV....2V Files: Project SCH&PCB - ORCAD 9.2 QUARTUS SRC for EPM570T100C5 IAR C SRC for AT91SAM7S64
miaobiao
- 秒表 数码管显示 采用verilog语言编写 Quartus II 9.0sp2 编译成功后生成的所有文件已包含-Digital display with stopwatch verilog language Quartus II 9.0sp2 successfully compiled all the files have been generated that contains
lab1
- 本实验主要练习使用Quartus II 9.1软件进行简单的FPGA 的I/O口实验，实验使用的是DE2开发板，使用芯片为EP2C35F672C6。本次实验的重点是掌握Quartus II 进行系统设计的流程、方法及调试技巧，并对DE2开发板的各个引脚的含义及使用有所了解。-This experiment and practice using the Quartus II 9.1 software is a simple FPGA' s I/O port experiments using
COUNT_ASYNC_4SUB
- 4位异步二进制减法计数器,利用QUARTUS II 9的CPLD/FPGA-4bit_count_asyn_sub
exp_micro_s
- 自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。 1.echo uart,接收rx_data,再回复！ 2.运行时请注意完整路径： D:\EXP\EXP_SOPCbuilder\exp_micro_s 3.UART数据输入问题？ 3.1 MODELSIM中w完信号后，run/restart一次。 3.2 设置clock=20ns。 3.3 命令行中输入uart_drive调出uart_
quartus-ii-9.0learn
- 用于VHDL的学习，文章内容为PDF格式简单易懂，适用于初学者-Used for VHDL study, the article content to PDF format simple and understandable, it is suitable for beginners
chengfaqi
- verilog语言编写的一个乘法器程序，是16位相乘！已通过仿真，用Quartus II 9.1 编写-a multiplier verilog language program, is 16 multiplied by! Through simulation, the Quartus II 9.1 to write
vga
- verilog语言编写的一个vga程序，是vga显示程序，用Quartus II 9.1 编写-a vga verilog language program is a vga display program, the Quartus II 9.1 to write
lcd
- verilog语言编写的一个lcd控制程序，是lcd显示程序，用Quartus II 9.1 编写-verilog language lcd control procedures, lcd display program written using the Quartus II 9.1
Code_NCO.zip
- 码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.
COUNTER
- a counter upward and donward until a certain number, designed on the quartus 2 web edition 9.1 simple code
abc
- 在Quartus II 9.1下开发FPGA/CPLD程序的使用教程操作笔记-Quartus II 9.1 developed under the operation of the FPGA/CPLD program using the tutorial notes
q_74ls138
- 在quartus II 9.1上用verilog原理图形式实现的74ls138功能的38译码器-38 of 74ls138 features achieve verilog schematic form in quartus II 9.1 decoder
swp
- 本文用Verilog语言设计实现SWP数字收发接口的电路设计，并用QuartusⅡ9.1完成调试和功能仿真。在我们的设计中，采用的是分模块的设计方法。设计过程中，我们将首先完成系统架构设计，明确各个分模块的功能。分别实现各模块功能后，再联合所有模块进行总体系统的调试和仿真，最终完成SWP数字收发接口的模块设计。-SWP paper implements digital transceiver interface circuit design using Verilog language desi
key0
- Keys Altera Quartus II 9.0 Altera MAX II While key is on then diod is on
CNTlum
- 使用Windows7 系统，quartus ii 9.1 软件，Verilog 语言 0到9的计数，并且亮度逐渐增大(count from 0 to 9,and the lum become more and more high)
mux21a
- 二选一，用于FPGA编程初学阶段，简单例子，使用时解压即可，Quartus II 9.0 (32-Bit)的应用(Two choose one, for FPGA programming beginner stage, a simple example, the use of decompression can be, Quartus II 9 (32-Bit) applications)
quartus ii 9.0 (1)
- 按钮您就能叫你家那叫奶奶看见了就能理解你(buttonjnknjknjnjnkjn)
chuzujifei
- 使用Quartus II 9.0编写的出租车计费系统源码，是课程设计大作业验证通过，可以直接仿真验证(The use of Quartus II 9 written taxis charging system source code, is the course design of large work verification through, can be directly simulated and verified)
Clock
- 本设计实现了一种基于FPGA的数字时钟设计，应用Verilog硬件描述语言进行数字电路设计，采用自顶向下的方法将电路系统逐层分解细化，设计数字时钟总体结构、各模块及相应具体电路。在Quartus II 9.0工具软件环境下编译、仿真。最后下载到FPGA实验平台进行测试。本数字时钟具有显示时间、通过按键校准时间、整点报时等功能。(This design realizes a digital clock design based on FPGA, uses the Verilog hardware