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SAR_Send
- 对altera的RS编解码IP核进行仿真，并且写了编解码的控制模块，用verilog实现，通过仿真，编码和解码功能正确。-test of RS code and RS decode,by using quartus ii9.0 with the IP core
Key_Xiaodou_Delay
- Verilog语言，Quartus II开发环境，按键延时消抖IP。-Verilog language, Quartus II development environment, key delay shake away IP.
PLL
- quartus II中IP核的使用案例，在程序里边调用了PLL核进行时钟的管理。-Quartus II IP core use cases, called in the program inside the PLL core clock management.
fftip_1k
- FFT IP核调用 VHDL语言 quartus -FFT IP core VHDL language called quartus
quartus12.0License
- quartus 12 的license，包括很多的ip核，杠杠的-Quartus12 license, including a lot of IP core,
MY_CAMARA_3_18_FIFO
- 基于QUARTUS集成环境开发的IP核，能够读取数据，并将其显示在数码管上-the IP core of fpga,can be used in embedded device
fir_test01
- 在quartus ii 环境下，用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
spiip
- 一个quartus的SPI接口的IP核-A quartus SPI interface IP core ...........................
A6850
- Altera Quartus Megacore of A6850. Published by Altera for free after the IP Megacore portfolio has changed.
A8237
- Altera Quartus Megacore of A8237 (DMA Controller). Published by Altera for free after the IP Megacore portfolio has changed.
A8251
- Altera Quartus Megacore of A8251 (UART). Published by Altera for free after the IP Megacore portfolio has changed.
A8255
- Altera Quartus Megacore of A8255 (3x8Bit PIO). Published by Altera for free after the IP Megacore portfolio has changed.
A8259
- Altera Quartus Megacore of A8259 (IRQ Controller). Published by Altera for free after the IP Megacore portfolio has changed.
pll
- 用quartus自带的ip核生成的pll代码-use the ip core from quartus ii to generate the programme of PLL.
ug_ram_rom
- This user guide describes the Altera megafunction IP cores that implement the following memory modes: ■ RAM:1-Port—Single-port RAM ■ RAM:2-Port—Dual-port RAM ■ ROM:1-Port—Single-port ROM ■ ROM:2-Port—Dual-port ROM Altera provides two IP c
my_second_fpga
- 用Quartus ii13.0写的二进制加法器，使用了IP核RAM，以及LCD显示，打开就能直接使用。-Using Quartus ii13.0 write binary adder, using the IP core RAM, and LCD display, open can be used directly.
LED
- 利用QuartusⅡ IPCore实现循环点亮LED.-Use Quartus Ii IP Core for recycling lit LED.
pic10
- 本文件夹里面的是实现pic10 CPU的全部verilog代码以及相应的测试脚本代码，当然有一些模块是在quartus中直接编辑波形测试的，所以没有响应的测试脚本文件。 tri_state_port的测试还未完成，test_pic10_status_reg.vt和test_pic10_tri_state_port2.vt都没有完成测试任务 其中有三篇文档： PIC10_RISC_Design.pdf:原文（verilog代码基本都来自原文，对一部分进行了改进），这篇文章写
spram
- verilog编写的spram，包含顶层模块，控制模块和spram本体，其中spram为Altera提供的ip核，已在quartus 16上运行通过(Verilog written in spram, including the top-level module, control module and spram ontology, where spram is the IP kernel provided by Altera, has been running on quartus 16)
PWM_last
- 在quartus中采用制作软IP核实现PWM波控制LED灯的显示(Using the soft IP in quartus to verify the display of the current PWM wave control LED lamp)