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Example-b4-1
- Altera基本宏功能的产生和实现方法.定制一个双端口RAM，DualPortRAM,Quartus II仿真器中做门级仿真,在ModelSim中对这个工程进行RTL级仿真.-Altera basic macro functionality of the generation and realization. Customize a dual-port RAM, DualPortRAM, Quartus II simulator to do gate level simulation, on t
quartusandmodelsim
- 本文档对quartus与modelsim运用操作描述十分详细，对初学者，会有很大帮助！-Quartus and modelsim this document on the use of operations described in great detail, for beginners, there will be a great help!
PN4
- 语言：VHDL 功能：该PN4序列的特点为将一个4位序列的前两位取异或，再让序列左移一位，用异或的结果作为序列的最后一位。序列周期是15，即15位伪随机序列。其中包括序列的产生模块和检测模块。对于误码检测，首先捕获相位。然后，规定测试的码的总个数，统计这些码中有多少个不能满足PN序列特点的，用计数器统计个数。如果发现误码过多，可能是相位失调，重新捕获相位，再进行误码检测。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function:
SRAM
- 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it
32Kfft
- 32KFFT例程，适用于Quartus II 5.0 or later。- This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later
ModelSimPSynplifyPQuartus-
- ModelSim+Synplify+Quartus fpga软件应用-ModelSim+ Synplify+ Quartus
Qartus2modelsim
- 在Altera Quartus 2下调用Modelsim进行仿真的实例代码-Invoked in the Altera Quartus 2 Modelsim simulation of the example code
sdr
- 全数字OQPSK解调算法的研究及FPGA实现 论文介绍了OQPSK全数字接收解调原理和基于 软件无线电设计思想的全数字接收机的基本结构，详细阐述了当今OQPSK数字 解调中载波频率同步、载波相位同步、时钟同步和数据帧同步的一些常用算法， 并选择了相应算法构建了三种系统级的实现方案。通过MATLAB对解调方案的 仿真和性能分析，确定了FPGA中的系统实现方案。在此基础上，本文采用Verilog HDL硬件描述语言在Altera公司的QuartusⅡ开发平台上设计
modelsim_testverilog
- 本代码提供了一个简单明了的利用quartus ii 9.0调用altera-modelsim的小程序，读者可以方便的利用代码来熟悉该调用操作，在极短时间内熟悉连个软件的应用。-This code provides a simple call to use quartus ii 9.0 altera-modelsim small program, readers can easily use the code to become familiar with the call operator, i
SetupModelSimQuartus
- 两篇资料中分别介绍了仿真软件ModelSim和Quartus 2的具体安装方法。-Two data simulation software were introduced ModelSim and Quartus 2 specific installation method.
verilog_Common_arithmetic
- 常用逻辑运算，加法器，乘法器及除法器的verilog语言，可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
dtrigger
- 常用触发器——D触发器的VERILOG语言描述，可用Quartus II 9.0 和modelsim环境实现。-Common triggers- D flip-flop of VERILOG language descr iption available Quartus II 9.0 and modelsim environment to achieve
modelsim6.2b
- 使用Modelsim进行仿真，包括前仿真，与后仿真，使用Quartus 调用Modelsim进行仿真-Using Modelsim simulation, including the former emulation, and after the simulation, the simulation using Quartus call Modelsim
exp_micro_s
- 自己在QuartusII9.1及Modelsim新版本中完成的microsequencer实例的工程文件。 1.echo uart,接收rx_data,再回复！ 2.运行时请注意完整路径： D:\EXP\EXP_SOPCbuilder\exp_micro_s 3.UART数据输入问题？ 3.1 MODELSIM中w完信号后，run/restart一次。 3.2 设置clock=20ns。 3.3 命令行中输入uart_drive调出uart_
Chapter-2
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-3
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-4
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-5
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-6
- 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
Chapter-7
- 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program