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f_add
- 在QuartusII软件环境下，运用VHDL语言编写的全加器的实现，包含仿真波形-In quartusii software. use vhdl languages of the implementation of a simulation waveforms
signal
- 在QuartusII软件环境下，运用VHDL语言编写的信号发生器的实现，包含仿真波形-In quartusii software. use vhdl language of signals to the realization of programme- and emulation waveforms
yt7132_clock
- 用VHDL语言编写的12/24小时时钟，利用EDA系统软件QuartusII环境下基于FPGA/CPLD的数字系统设计方法-VHDL language with the 12/24 hour clock, the use of EDA software QuartusII environment based on FPGA/CPLD design of digital system
model_adder
- 包括一个基于Quartusii的加法器工程，以及基于ModelSim的前仿真、综合后功能仿真和布局布线后时序仿真的完整例程及testbench文件，吐血推荐，非常有用！-Includes an adder based Quartusii works, and the first based on ModelSim simulation, synthesis functional simulation and post layout timing simulation after complete
ethmac
- ethmac IP CORE VHDL IN QUARTUS-ethmac IP CORE VHDL IN QUARTUSII
i2c
- I2C IP CORE Verilog quartus-I2C IP CORE Verilog quartusii
spi
- SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
uart
- uart IP CORE Verilog quartus-uart IP CORE Verilog quartusii
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii
VHDL_1602-LCD
- 使用VHDL语言，以纯逻辑的方式驱动1602LCD显示屏显示指定字符.通过quartusII软件进行开发。 -VHDL for 1602 LCD display.
EPM240-QuartusII-ModelSim
- quarter ii调用modelsim，在fpga仿真时，为了能减少器件本身对时序的影响，我们一般采用第三方的仿真软件如MODELSIM来验证时序的正确性-quarter ii call modelsim, in fpga simulation, in order to reduce the impact of the timing device itself, we generally use third parties to verify the simulation software,
VHDL-lecture
- VHDL语言实验教程，以及QuartusII教程-Experimental Course VHDL, and QuartusII Tutorial
Max_Plus_II-_tutorial
- Max+plusII(或写成Maxplus2,或MP2) 是Altera公司推出的的第三代PLD开发系统(Altera第四代PLD开发系统被称为：QuartusII，主要用于设计新器件和大规模CPLD/FPGA).使用MAX+PLUSII的设计者不需精通器件内部的复杂结构。设计者可以用自己熟悉的设计工具（如原理图输入或硬件描述语言）建立设计，MAX+PLUSII把这些设计转自动换成最终所需的格式。其设计速度非常快。Maxplus2被公认为是最易使用，人机界面最友善的PLD开发软件，特别适合初学者
thefirstexampleforQuartuslearners
- quartuslearners 学习 入门 软件应用-quartusII study
REPIC_project
- Reactive PIC 16F84A code using Esterel..QuartusII compilation
pll
- quartusII环境下用Verilog语言的数字锁相环的实现。- In quartusII environment digital PLL implementation using Verilog language .
V35interface-communicate
- V.35接口与E1接口之间转换的基本原理,介绍了E1信道分时隙通信的基本过程，叙述了基于FPGA用VHDL和QuartusII来仿真本系统设计与实现的过程。-V.35 interface and E1 interface to convert between the basic principles of E1 channel introduces the basic process of communication sub-time slot, described by VHDL and FP
clock
- 在QUARtusII 环境下开发 应用VHDL语言编程 编写的时钟程序-QUARtusII environment in the development and application written in VHDL language programming clock program
Design-AND-gate
- 通过应用QUARTUSII开发软件对与门的设计（二输入）和D触发器的设计。 -QUARTUSII development through the application of software and door design (two inputs) and the D flip-flop design.
Multiplexer-Description
- 通过应用QUARTUSII开发软件对二选一多路选择器进行设计并运行结果-Software development through the application of QUARTUSII choose one of two multiplexer design and operation results