搜索资源列表
靳远-源程序
- 几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码-several VHDL source code, and in my preparation of a five pipelined RISC CPU code
embedded_risc
- 一个嵌入式RISC CPU 的Verilog 设计源码,可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
16_risc_cpu
- 一个支持精简指令的16位的risc cpu,可综合-a directive to support the streamlining of the 16 RISC CPU can be integrated
alu
- mcu,risc cpu Verilog源代码-mcu,risc cpu Verilog
RISC_SPM
- 简单risc cpu设计,本人通过书中的代码,又加了一些,已通过仿真。-Risc cpu simple design, I code by the book, but also added some, has been through simulation.
cpu-design
- VHDL设计的一个可综合的精简指令集的CPU,加上外围模块,类似与51单片机,当然还缺少很多功能,只是雏形,供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
zxcpu
- 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步,系统使用一个主存单元。处理器指令字长16位,包含8个通用寄存器,1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位,取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA,STA,MOV,MVI,ADD,SUB,AND,OR,JZ,JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a R
A-RISC-Design
- RISC设计:MIPS指令集控制器核,详细介绍一款32位risc-cpu。-A RISC Design:Synthesis of the MIPS Processor Core
cpu
- 用verilog实现的一个32位RISC处理器,能够实现简单的移位、加法等基本操作。-Verilog implementation with a 32-bit RISC processor to achieve a simple shift, addition and other basic operations.
RISC_cpu
- 基于RISC结构的8位微处理器的verilog源代码,很好的东西。-8-bit RISC-based microprocessor architecture verilog source code, a good thing.
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核,该CPU具有32位数据宽度,5级流水线结构和指令预判和中断处理功能,适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
RISC---8
- 集成RISC-CPU芯片设计,很实用的程序,对初学FPGA的同学有很大的帮助奥-Integrated RISC-CPU chip design, very practical program, beginner FPGA classmates help Austrian
cpu-risc
- wb_switch,cpu设计,精简指令cup设计-wb_switch,opencore,risc cpu design。
16-CISC-CPU-design
- 16位精简指令集的CPU设计,有完整的步骤和原程序可供学习-16-bit RISC CPU design, complete steps and the original program for learning
8Bit-CPU
- 8 Bit RISC CPU implementation in VHDL
CPU
- 4位精简指令集的cpu设计,是数字电路与逻辑的课程设计,对于学习微处理器和数字电路的同学还是很有帮助的-4 RISC cpu design, digital circuit and logic of curriculum design, microprocessors and digital circuits for learning or helpful for students
RISC-CPU-
- 用VHDL语言实现32位CPU的各种运算功能,熟悉32位CPU各模块的工作原理,熟悉流水线数据通路和控制单元的工作原理从而熟悉CPU的工作机理。-Mac circuit realization
Mini-Risc-core
- 这个源码是RISC型CPU处理器,正常动作,给很大帮助想做CPU处理器的人。-This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the PIC 16C57 Microchip.
cpu
- 一份精简指令cpu源代码,用verilog编写,已经通过仿真验证,可以模块化移植。-This is a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
riscCPU
- 实现 八位RISC cpu 含有V文件和 testbents测试文件(Realization of eight bits RISC cpu)