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spi_verilog_master_slave_latest.tar
- spi 的verilog rtl 代码, 包括整体仿真环境,测试码等(spi master or slave verilog rtl code)
Synopsys SCL 10.9.3
- 后端综合软件design compiler将verilog源码,RTL文件转变成电路并实施优化
8051Core
- 8051 Core Verilog RTL IP Code
apb_timer.tar
- 是基于apb总线下的timer外设的rtl代码,主要包括apb_timer的master逻辑verilog,以及相应的开发文档,包括寄存器的描述,功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the descr