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SDRAM_control_design
- 一个SDRAM控制器的参考设计vhdl语言，包含了全部逻辑功能代码以及约束文件，包括一些综合布线后的文件和波形，有较高的参考价值。-A SDRAM controller reference design vhdl language contains all logic code as well as the constraints file, including files and waveform integrated wiring, there is a high reference val
sdr_ctrl
- SDRAM控制器源码 Verilog描述-SDRAM controller Verilog source descr iption
DDRSDRAM
- 基于VHDL的DDR SDRAM控制器的设计，实现数据的读写功能，迸发长度分为2，4，8-Based on the VHDL DDR SDRAM controller design, implementation of data read and write capabilities, burst into the length of 2, 4, 8
my_test_rw_pack9
- 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclon
DDRSDRAMverilog
- 本文介绍了sdram控制器的。本文附上了介绍文档，具有详细的说明。-This article describes the sdram controller. The attached introductory document, a detailed descr iption.
Sdram_Control_4Port
- 文档介绍了SDRAM控制器，带有四个fifo,希望对初学者有一定的帮助。-The document describes the SDRAM controller with four fifo some help for beginners.
sdram1
- 定制sopc系统。使用sdram控制器。在nios ide上执行存储器的读写操作。-To customize sopc system. Use sdram controller. In the the nios ide perform memory read and write operations.
Sdram_Control_4Port
- SDRAM控制器的verilog源代码实现-SDRAM controller Verilog source code to achieve
ddr2_v5
- 基于FPGA v5的ddr2-sdram控制器的设计verilog-Based on FPGA v5 of ddr2-sdram controller design verilog
fifo1k_32
- vhdljichu,完成vhdl中对sdram控制器的功能-vhdljichu, completed in vhdl sdram controller functions for
61EDA_C915
- altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
SDRAM_verilog@tequan
- 本资源是特权同学编写的sdram控制器，包括数据读写，串口输出，很有学习价值-This resource is privileged students write sdram controller, including data read and write, serial port output, is worth learning
SDRAM_Modelsim
- 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
DDR3-SDRAM-Controller
- DDR3的控制器（并带有Testbench），可烧录到FPGA中对内存进行读写，相关技术人员可在该代码上修改用于其他场合-DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions
sdram_latest.tar
- sdram 控制器 verilog 源码-verilog source of sdram control
sdram_verilog
- 基于verilog语言的SDRAM控制器-SDRAM controller based on verilog language
SDRAM_CONTROL_DE2
- 基于Altera公司的Cyclone II 2C35芯片和SDRAM芯片IS42S16400的sdram控制器（教学用）-Based on Altera Cyclone II 2C35 chips and SDRAM chips IS42S16400. the code realize a the sdram controller (for teaching)
sdram_top
- 适合初学者的sdram控制器，包含初始化、控制功能、命令写入基本模块，有详细注释。-Sdram controller suitable for beginners, including initialization, control, command writes the basic module, with detailed notes.
testsdram
- 一个用Verilog语言编写的SDRAM控制器源码, 逻辑清晰, 结构合理!-SDRAM controller is a source code in Verilog language, logical, reasonable structure!
mem_interface_top_ddr_controller_0
- 在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。-DDR controller