搜索资源列表
10010
- Verilog状态机设计-10010序列检测器-Verilog state machine design-10010 Sequence Detector
JIANCHE
- 本设计是一个序列检测器，能够检测11位长的系列信号，根据需要可适当扩展其序列长度-The design is a sequence detector, can detect a long series of 11 signals, according to the needs may be appropriate to expand its sequence length
check
- 用Verilog实现的序列检测器，可以检测出任意规定序列-Verilog implementation using the sequence detector
sequencedetector
- verilog code for 3 bit sequence detector
sdmrbeh
- This code implements the behavioral modelling of a Moore type sequence detector to detect the sequence 1010. The code is a quartus project file
seqdet
- 串行序列检测器，以得到modelsim仿真波形，用verilog编写。-Serial sequence detector to get modelsim simulation waveform, prepared with verilog.
seqdetector1001.v.tar
- 1001 sequence detector in verilog code for mealy state machine
Sequence-Detector-State-Machine
- 状态机序列检测器设计，包含程序在内，该程序是检测1101-Sequence detection state machine design, including the program included, the program is to test 1101
Lab5(sequence-detector)
- sequence detetect on spartan 3e...vhdl code
detector
- 序列检测器，实验题第一题，懂的人都懂得，可以实现对1101的检测，使用状态机-Sequence detector
sequence
- 利用Basys2 FPGA 开发板实现简单的序列检测器-Basys2 FPGA development board to achieve a simple sequence detector
A-Verilog-Model-of-Universal-Sequence-Detector.ra
- a verilog model of universal seq detector
VHDL-to-design-detector
- 用VHDL语言设计一个序列“111010”的检测器和该序列的发生器-VHDL language " 111010" to design a sequence detector and the sequence generator
sequential-detector
- 用状态机实现序列检测器的设计，并对其进行仿真和硬件测试-With a state machine sequence detector design, and its simulation and hardware testing
10-sequence-detector
- 本系统采用实验箱的48MHz时钟作为输入时钟，将其分频得到计数器计数频率和序列检测器检测序列频率-The system uses a 48MHz clock experimental box as the input clock, to get the counter frequency divider and serial sequence frequency detector
detector-(1110010)
- 序列检测器（1110010）设计 ，Quartus 10.0+modelsim 6.5SE联仿真报告形式-Sequence Detector (1110010) designs, simulation with Quartus 10.0+ modelsim 6.5SE ， reports
Sequence-Detector
- 序列检测器，开写为两个always语句，即为两段式有限状态机。将组合部分中的判断状态转移条件和产生输入再分开写，则为三段式有限状态机。 二段式在组合逻辑特别复杂时适用，但要注意需在后面加一个触发器以消除组合逻辑对输出产生的毛刺 。三段式描述方法虽然代码结构复杂了一些，但是换来的优势是：使FSM做到了同步寄存器输出，消除了组合逻辑输出的不稳定与毛刺的隐患，而且更利于时序路径分组，一般来说在FPGA/CPLD等可编程逻辑器件上的综合与布局布线效果更佳。-Sequence Detector
sequence
- sequence detector is used to detect sequence a given input pattern-sequence detector is used to detect sequence a given input pattern
sequential detector
- verilog 固定序列检测器，能够检测10111序列，波形无误。适合Verilog初学者学习(Verilog fixed sequence detector)
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)