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spi_slave
- spi(serial peripheral interface) slave unit with Verilog-HDL
SPI_fpga_w_r_sigle
- verilog fpga spi slave 收发测试 有简单的协议 modelsim仿真通过 -simple protocol modelsim verilog fpga spi slave transceiver test simulation by
spi-verilog
- 用Verilog来实现SPI接口电路逻辑，实现主机与从处理器的通信-SPI interface circuit is implemented in Verilog logic between master and slave processor communication
SPI
- verilog slave with simulation mode and file pdf
V2.tar
- SDIO slave, written in verilog, does not support SPI mode.
spi_rtl
- 支持主从模式的、可综合的SPI verilog代码-Supports master and slave mode SPI communication module can be integrated RTL code
vSPI-master
- Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter