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mem_ctrl.tar
- verilog 写的 memory controller ，可以控制SDRAM SRAM NOR
S3C44B0X中文技术文档
- 介 绍 三星的S3C44B0X 16/32位RISC处理器被设计来为手持设备等提供一个低成本高性能的方案。 S3C44B0X提供以下配置：2.5V ARM7TDMI 内核带有8Kcache ;可选的internal SRAM;LCD Controller(最大支持256色STN，使用LCD专用DMA)；2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO； 2-ch gener
CS8955TV_source_code.rar
- CS8955控制TV软件。用MCU做模拟电视的控制。,CS8955+TV+TNJ7355(tuner).The CS8955 micro-controller is an 8051 CPU core embedded device targeted for LCD Monitor, LCD TV, Home Appliance, or Consumer Products application. The CS8955 is pin-out compatible with MCS-51
SRAM_controller
- 对于想编写sdram控制器的人来说，值得借鉴-Sdram controller would like to prepare for the people, to learn
lan91c111_an96
- 该资料为lan91c111芯片的英文原版application note，提供了使用LAN91C111进行开发所需要的软件、硬件设计、功能测试等资料。LAN91C111为SMSC公司生产的以太网控制芯片，为第三代高速以太网连接提供嵌入式解决方案。-The application note of LAN91C111.The SMSC LAN91C111 is a 32/16/8-bit Non-PCI Fast Ethernet controller that integrates on one
ZBTSRAM
- 高速同步SRAM控制器参考设计VHDL代码-High-speed synchronous SRAM controller reference design VHDL code
sram_controleur_top
- Sram controller with 6 commande ports
EMCSIMoutput
- External SRAM Memory Controller Design Simulation Results
SRAM_Controller
- altera 大学计划 程序包的sram controller ip-altera University Program package sram controller ip
040402~~
- 虽然与SRAM相比，SDRAM需要额外的控制逻辑，有更复杂的时序要求，需要定时刷新，但是由于SDRAM具有单位空间存储容量大和价钱便宜的优点，因而被许多的嵌入式开发者所青睐。为此，针对这种情况，必须设计SDRAM控制器。为了降低系统成本，本课题采用FPGA技术，并使用VHDL语言研究了FPGA与SDRAM的存储器接口实现问题。-Abstract In order to expand the SDRAM’S storage capacity of the TS一101 processor，a me
NUC501_datasheet_A1.4
- 适合使用NUVOTON nuc501 做开发的参考。-The NUC501 is an ARM7TDMI-based MCU, specifically designed to offer low-cost and high-performance for various applications, like interactive toys, edutainment robots, and home appliances. It integrates the 32-bit RISC CPU w
SRAM_test
- SRAM的一个控制器，内附文档说明。设置地址和输入数据，完成写功能，再次输入地址，完成读功能。-An SRAM controller, included documentation. Set the address and input data, complete the write function, enter the address again to complete the reading function.
VHDLSDRAMcommand.vhd
- 基于fpga的实现sram控制器的vhdl源代码，非verilog-sram controller VHDL source code
DDDRR_SDRAM_cD
- DDR SRAM控制器的verilog完整设设计文档（包含有完整的verilog源代码）， -DDR SRAM controller the verilog complete set design document (contains the complete source code verilog)
src
- 异步SRAM控制器，已经在DE2板子上测试可用，测试频率50MHz。-Asynchronous SRAM controller, has been on the DE2 board test available test frequency 50MHz.
SRAM_Control
- common sram controller
elevator-verilog-code
- SRAM CONTROLLER CAN GIVE YOU CORRET IDEA ABOUT VERILOG
controleur_sram
- SRAM controller A Sample Exemple -SRAM controller A Sample Exemple
sram_16bit_512k
- FPGA 的sram controller -it is a certifed sram controller
ahb_sramc
- 基于AHB总线的sram控制器，带有memory bist(SRAM controller based on AHB bus)