搜索资源列表
SRAM@DMA实验
- ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
ZBT SRAM控制器参考设计vhdl_xilinx
- ZBT SRAM控制器参考设计，xilinx提供的VHDL源代码-ZBT SRAM controller reference design for Xilinx VHDL source code
SRAM
- 是一个基于VHDL的SRAM程序，很有代表意义，下下吧
SRAM
- 静态随机存储器(SRAM)设计VHDL代码，已经生成的了
SRAM
- FPGA控制ＳＲＡＭ61LV25616 vhdl源程序．
sram+lcd
- 用vhdl格式写的sram源代码，把扩展名txt改为.v即可
sram
- FPGA向SRAM中写入数据(VHDL编程)，包含通用fifo，sram等
de2_lcm_ccd_sram
- 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
IS61WV51216
- iss simulation model for 512KX16 SRAM
code_20-08-09
- CPLD Interface code with SRAM
sram_saa1117verilog
- 图像采集、存储控制verilog源代码，fpga控制SAA1117,采集数据存储到sram，仿真编译测试都能通过-Image acquisition, storage, control verilog source code, fpga control SAA1117, collecting data to sram, simulation tests can be compiled by
sram
- sram vhdl code. Very helpful
63535309sram
- verilog编写的读写SRAM的源码，包括sram的读写控制-SRAM read and write verilog source code written in, including the sram to read and write control
IS64LV6416L
- Asynchronous SRAM IS64LV6416L modelsim仿真模型-Asynchronous SRAM IS64LV6416L Verilog model
SRAM
- SRAM源代码，VHDL语言编写，载入可编译，需要的-SRAM source code, VHDL language, incorporated in the compiler, we need to see
sram
- 数据存储和读取电路以一个双端口SRAM为中心，用二进制计数器产生存取地址、以十进制计数器产生欲存储的数据，读出的数据经过LED七段译码，送LED数码管显示-Data storage and reading circuit in a dual-port SRAM as the central access address generated using a binary counter to generate For decimal counter data stored, read out th
SRAM
- 语言：VHDL 功能：利用VHDL编程，实现FPGA对SRAMIS61LV24516的读写操作。由于是针对IS61LV24516型号进行读写的，如果不是此型号的SRAM需要对程序进行时序修改。 仿真工具：modelsim 综合工具：quartus -Language: VHDL function: the use of VHDL programming, FPGA on SRAMIS61LV24516 read and write operations. Because it
zbt_test
- zbt sram测试VHDL程序，实现了FPGA与ZBT SRAM之间的接口控制，在FPGA内能实现对ZBT SRAM读写-vhdl program for ZBT SRAM test
SRAM
- 2. FSM is frequently used to design SRAM controller. Given the bubble diagram of a SRAM controller and its state-and-output table as shown below
sram
- SRAM的VHDL设计，设计了一个具有4位地址线，8位数据线的SRAM，读写功能独立-SRAM VHDL design, the design of a 4-bit address lines, 8 data lines of SRAM, read and write functions independent