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shuzipaobiao
- 在ISE环境下用Verilog HDL写的一个简易的数字跑表，最大量程为60分钟，精确到毫秒级，有复位键和暂停键。-In the ISE environment, using Verilog HDL to write a simple digital stopwatch, the maximum range is 60 minutes, accurate to the millisecond, the reset button and pause button.
shuzipaobiao
- 一个关于数字跑表的小程序代码，verilog实现，并通过仿真。-A digital stopwatch on a small code, verilog implementation, and simulation.
timer
- verilog秒表fpga 4位数码管显示-verilog digital display stopwatch 4
sclock
- 一个verilog实现的秒表程序，项目文件-Verilog implementation of a stopwatch program
digital_clock
- verilog digital clock.四位 有计时器 有秒表 。是学生作业。 原创。 适合初步学习verilog的学生。 -verilog digital clock/4 bits/ up_down/stopwatch
display_combine
- 这是学生做的Verilog HDL 作业。 是一个数字钟。 有时钟，秒表等功能。 原创。-This is the Verilog HDL students to do the job. Is a digital clock. A clock, stopwatch and other functions. The original.
paobiao-_verilog
- 数字跑表，硬件表述语言Verilog 实现，测试功能全 -Digital stopwatch, expression language Verilog hardware implementation, testing, full-featured
watch
- verilog 完全集合了电子表所拥有的功能，计时，调时，秒表，闹钟四个功能-verilog completely owned by a collection of spreadsheet functions, timing, tone, the stopwatch, alarm clock features four
Lab3
- This is stopwatch writen in Verilog HDL. Also there is code for 7-segment display decoder. I tested it on ALTERA de2-115 development and education board.
paobiao
- 这个程序是用verilog语言下的数字跑表实验，经测试，好用。-This program is a digital stopwatch experiments under the verilog language, tested, easy to use.
verilog_example
- verilog实例，多路器，除法器，数字跑表的多种实现方法-verilog example, the multiplexer, a divider, a digital stopwatch many implementations
stop-watch
- stopwatch with verilog it counts up and reset
paomiao
- 用Verilog编写的跑秒程序，最大时间30秒，适合于各种场合的倒计时。-Written using Verilog stopwatch program, the maximum time of 30 seconds, the countdown is suitable for a variety of occasions.
miaobiao
- verilog 的 48M频 出入秒表，带停止启动 清零功能-the verilog of 48M frequency of access stopwatch, with stop start clearing the
miaobiao
- 这是用verilog写的一个关于秒表实现的程序，已在DE2上成功实现-Verilog write a stopwatch to achieve the program has been successful on the DE2
v-miao
- verilog的秒表计算和显示，详细的代码和分析，逻辑清楚，适合初学者学习。-Verilog stopwatch calculation and display, detailed code and analysis, logic clear, suitable for beginners to learn.
EXP6
- 基于Verilog 的实现秒表的程序 先要安装Quartus II 6.0 可用看到时序仿真-To achieve a stopwatch program Verilog to install Quartus II 6 can be used to see the timing simulation based on
another
- 这是一个用数码管显示的verilog语言描述的数字秒表，且引脚已经分配完毕，基于DE2，可直接下载到板子上使用-This is a digital stopwatch with digital display verilog language described, and the pins have been fully allocated, based DE2, can be directly downloaded to the board
runningclock
- verilog HDL实现跑表设计，开发环境为xilinx，fpga芯片为spartan系列。-verilog HDL the Stopwatch design and development environment for the spartan xilinx, fpga chip series.
miaobiao
- 基于Max+plus2软件的Verilog VHDL语言的按键控制数码管显示秒表-Based on Max+plus2 software Verilog VHDL language button control digital display stopwatch