搜索资源列表
Timer
- Verilog编写的多功能秒表，Quartus仿真及硬件测试通过。-Verilog prepared by the multi-function stopwatch, Quartus simulation and hardware testing through.
mb
- 基于Proasic3 startkit 开发板，用verilog语言描述的一个秒表计数器。-Based the ProASIC3 StartKit development board, using Verilog language descr iption of a stopwatch counter.
clock
- 用 Verilog HDL 设计一个多功能数字钟，包含以下主要功能： 1） 计时，时间以 24 小时制显示； 2） 校时； 3） 闹钟：设定闹钟时间，可利用 LED 闪烁作为闹钟提示； 4） 跑表：启动、停止； 5） 其他。-Using Verilog HDL design a multi-functional digital clock contains the following main functions: 1) time, the time is displayed
miaobiao
- 用verilog语言在FPGA上实现秒表数码管显示-Implemented on FPGA using Verilog language stopwatch digital display
miaobiao
- 由verilog编写的秒表程序，按键控制 按下一键秒表停止 按下另外一键 秒表又运行-Verilog prepared by a stopwatch program, press a button control key pressed another button to stop the stopwatch stopwatch and run
lab16
- 利用verilog设计一个数字秒表电路。可以通过按键开始计时，计时完毕，清零设定。-Use verilog design a digital stopwatch circuits. Can be key will begin counting is completed, clear the settings.
wtut_ver.ZIP
- 码表程序，完整的verilog工程文件，完整的工程设计流程，包含时序约束，ip核的嵌入，以及DCM模块的使用-Stopwatch program, complete verilog project file, complete engineering design process, including the timing constraints, ip nuclear embedding, as well as the use of DCM module
paobiao
- 本源码是用verilog编写的FPGA程序，其中包括了数字跑表模块和RS触发器模块。-The source code is written in verilog FPGA programs, including digital stopwatch module and the RS flip-flop modules.
paobiao
- ISE仿真平台下建立的用verilog语言实现的简易数字跑表工程-Simple digital stopwatch works with verilog language of the establishment of the ISE simulation platform
miaobiao
- 一个精确的秒表，显示在数码管上。对于初学者使用verilog有很大的帮助，同时注释很详细。-An accurate stopwatch displayed on the digital pipe. For beginners verilog a great help, and very detailed notes.
exercise
- 使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。-Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.
Timer
- 基于verilog xilinx spartan 3e100的秒表计时器-Based verilog xilinx spartan 3e100 stopwatch timer
stopwatch_c
- 用Verilog写出来的秒表。可以实现计时、暂停、继续、清零等基本功能。还能实现简单的菜数字游戏。-Written using Verilog stopwatch. Can achieve timing, pause, continue, cleared and other basic functions. Also enables simple dish numbers game.
multifunction_digita
- 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-There FPGA-based design and implementation of multi-functional digital clock containing detailed Verilog HDL source code and its function are: time setting, time display, stopw
EX4V1.1
- 该设计是基于Verilog HDL的秒表。此设计是在Altera的Cyclone II系列的FPGA上验证过了。能够实现精确计时。-This design is a stopwatch based on the Verilog HDL. And it has been verified on the platform of Cyclone II s FPGA of Altera. Finally it can achieve accurate timing.
sencond_counter
- 在ise14.7开发环境下，用Verilog编写的秒表程序，其中通过状态机实现数码管的动态显示-In ise14.7 development environment, using Verilog prepared stopwatch program in which the state machine implementation through dynamic digital tube display
clock_display
- 自己用verilog语言编写的数字钟程序，能在Alter公司的DE0板上完美运行，能时间计时，日期，闹钟，秒表的功能。 欢迎交流学习。-The digital clock program which developed by verilog language can run at Alter DE0 board, to the time time, date, alarm clock, stopwatch function.
second
- 利用Verilog HDL语言进行数字系统设计实现秒表的设计，涵盖原理图设计、文本设计以及进行波形仿真，并有对应的报告。报告中还包括BCD/7段译码集成电路74LS47仿真实验、单管分压式稳定工作点偏置电路仿真实验和8路智力竞赛抢答器电路设计-Use Verilog HDL language design and implementation of digital systems design stopwatch, covering schematic design, text, design,
start_lab4
- 用Verilog设计一个时间基准电路和带使能的多周期计数器，并在此基础是设计一个简单的秒表0.0-10.0计数- Verilog design with a time reference circuit and with enable multi-cycle counter, and on this basis is to design a simple stopwatch count 0.0-10.0
suzipaobiao
- 这是用verilog编写的数字跑表 ，里面包含有程序和仿真图 通过编译-It is written in verilog digital stopwatch, which contains a program to compile and simulation map