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jing
- 用VHDL语言编程一个具有秒计时，定时的数字时钟，其中包括程序，图示，仿真结果及报告。-VHDL programming a stopwatch, digital clock timing, including procedures, icon, simulation results and reports.
miaobiao
- 利用vHdl描述语言实现的60秒秒表。能够实现60秒的计时功能-Use of vHdl descr iption language implementation 60 seconds stopwatch
seconds-counter
- 在EP2C5T144C8开发板上编的一个VHDL源程序，相当于一个秒表，读数可在4个数码管上显示，通过按键可暂停计数，可继续计数-In EP2C5T144C8 development board this a VHDL source code, the equivalent of a stopwatch, reading on the four digital tube display, can suspend count by buttons, can continue to count
matlab
- vhdl learning materials，-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
secnew
- 基于FPGA的数字秒表设计。用VHDL语言设计数字秒表。-FPGA-based design of digital stopwatch. Design using VHDL digital stopwatch.
finaldesign_watch
- 基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for th
timer
- 基于VHDL语言的一个简单秒表，包含按键消抖模块、数码管译码、计时器等模块。直接适用于basys2和nexys3两个开发板。更改ucf文件后适用于其他开发板-A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards
shuzizhong
- 基于CPLD的智能数字时钟VHDL设计，能实现时钟、秒表、闹钟、定时等功能-ntelligent digital clock CPLD VHDL-based design enables the clock, stopwatch, alarm clock, timer, and other functions
exp18
- 这是一个vhdl的交通灯程序，可以实现两个方向间红、黄、绿灯之间的亮灭转换，同时还有秒表的计数、显示功能，为学习vhdl的人提供一定的技术参考。-This is a vhdl traffic lights procedures can be achieved between the two directions of red, yellow, green light off between the conversion, as well as the stopwatch count, displ
MB
- 基于VHDL语言数字秒表设计,在FPGA实验平台下开发-Digital stopwatch design based on VHDL, FPGA experimental platform under development
jishu
- 基于VHDL的计时秒表 59分59秒59 具有计时暂停功能 通过数码管显示-Timing stopwatch 59.59.59 with timing suspended through digital tube display please enter the text to be translated
JiShuQi
- 实现了一个秒表计数器，输入为2MHZ时钟，使用VHDL语言实现-It implements a stopwatch counter input 2MHZ clock, using VHDL language
VHDLtime
- 实现秒表设计，实现秒、百分秒之间的相互切换，初级VHDL代码-Realize stopwatch design, implementation seconds, percentage of seconds to switch between each other, the primary VHDL code
miaobiao
- 使用VHDL\FPGA实现秒表的设计，包含所有源码。-Use VHDL\FPGA to achieve a stopwatch
practise
- FPGA实验板设计一个数字跑表。根据题目要求利用VHDL语言设计出一个系统，包括分频器，开关消抖，使能控制，计数器，锁存器，数据选择器及显示译码器。-FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, c
ELECTRONICCLOCK
- VHDL语言设计的电子钟，并且有暂停功能和清零功能的按键实现，并且带秒表-VHDL language design electronic clock, and there is a pause function and achieve clear function buttons, and with stopwatch
VHDL_paobiao
- 用VHDL语言设计一个跑表，计时范围为59.99秒。-Write a time range using VHDL language to 59.99 seconds in the stopwatch
swfsm
- stopwatch的FSM状态机的代码，可供初学者学习参考如何编写状态机-the finite state machine vhdl code for the simple stopwatch file
VHDLstopwatch
- 采用vhdl硬件描述语言实现的秒表计时器程序源码及顶层电路设计图，实现了计时器，数码管显示，按键控制及蜂鸣器等功能-Using VHDL hardware descr iption language to realize the stopwatch timer program source code and top-level circuit design, the timer, digital tube display, control buttons and a buzzer functio
chronometer
- You can use this to build a stopwatch on a nexys 3 board in VHDL.