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doublefloat_RAM
- 使用verilog编写的一个双浮点RAM，支持对字、字节、半字、双字的读写，包含testbench和wave.do文件-Use verilog to implement a double float RAM, supporting the read and write of halfword,byte,word,double word. It includes the testbench and wave.do
fibonacci_matlab_verilog
- 使用Matlab和Verilog实现fibonacci序列，包括源代码和testbench-use matlab and verilog to realize fibonacci sequence,including source code and testbench
ReadFsm
- VHDL小程序，read FSM。可以作为VHDL一次作业使用。包含测试文档testbench。-VHDL applet, read FSM. A job can be used as a VHDL。VHDL code and testbench.
4bit-adder_verilog
- 4位全加法器的modelsim工程带testbench-Four full-adder modelsim project with testbench
2.5
- 8位bcd码计数器带testbench工程，好用-8-bit bcd counter with testbench code works, easy to use
3.1
- 加法树乘法器带testbench好用的工程-Adder tree multiplier with testbench-use project
3.2
- 查找表乘法器带testbench好用的工程-Easy to use look-up table multiplier works with testbench
3.3
- 布尔乘法器带testbench好用的工程啊-Boolean multiplier works with testbench nice ah
3.4
- 移位除乘法器带testbench好用的工程-Useful addition to the shift multiplier works with testbench
decoder
- It is a simple decoder created using vhdl in xilinx ise.It will helpful for beginners to create deocder using this.testbench for simulation is also created.
TIMER_tb_v1
- testbench for the alarm clock circuit
fpga_assignment1
- 这是由简单串行转并行的一个verlog程序，还带testbench，有一张仿真的图片在里面。软件用的是Quartus II9.1 Web Edition。-This is from the simple serial turn a verlog parallel programs, but also bring testbench, and a simulation pictures in it. Software is used II9.1 Web Quartus happen.
lfsr
- lfsr.vhd - The top module in the project. lfsr_pkg.vhd - The package file used for supporting the lfsr top module. lfsr_tb - A testbench code for lfsr module. manual.pdf - A short documentation on this project. README.txt - A short descr i
Part-2-DWT-haar-using-VHDL
- Part 2 testbench for Discrete wavelet transfrom implementation in VHDL language Haar Filter
Writing-Testbenches--
- 介绍如何使用system verilog搭建testbench。-introduce how to use the system verilog to writing testbench
lattice_i2c
- lattice公司的i2c核rd1006 包含testbench测试模块-lattice' s i2c core rd1006 (includes test module testbench
eprom
- Verilog编写的eprom仿真模型，包括testbench文件和测试用bin文件-Write eprom Verilog simulation model, including the testbench file and bin file for testing
Multiplieur-signe
- VHDL code of a signed mixer with a testbench !
inverseuse_ex1
- this a inverse gate with lot s of other gates and testbench for novice-this is a inverse gate with lot s of other gates and testbench for novice
Cadence-Encounter
- 8x8 mulitplier. created this file using the midelsim softwre. Tested and simulated. Great waveform, so the testbench is included also. Does anybody knkow how to make a 16x16 arrray multiplier?