搜索资源列表
get_e_de
- 模糊控制器 误差生成模块.V文件及testbench文件-Fuzzy controller error generation module .V file and testbench files
Modelsim_Steps_-to_-run_-testbench
- Writing test bench in using VHDL.
TEXIO
- TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
Testbench_SR_SerIn
- Testbench for Shift Register, Serial in Parallel out
tb
- fft128_64的testbench文件，用于测试fft的正确性。已验证其正确性，喜欢的就拿走啦-Fft128_64 testbench files, used for testing the correctness of the FFT
DFF12
- 简单modelsim testbench测试工程，包含源码和testbench文件-Modelsim testbench simple test project, including source code and testbench files
testbench_top_level.vhd
- testbench for top level, vhdl, audio synthesizer, top level
QAM_verilog
- 基于FPGA的16QAM，用verilog编写，其中DDS为自己编写，含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
testbench
- 这是基于xilinx ise软件中pci核的仿真程序。文件包括激励程序，顶层程序。可以用于modelsim仿真-This is based on xilinx ise software pci core simulation program. Files include incentive program, the top program. It can be used to simulate modelsim
MyFFT
- 该程序可实现基于IP核的FFT算法，TESTBENCH用TEXTIO输入输出数据-The program can achieve FFT algorithm based on IP core, TESTBENCH based on TEXTIO input and output data
CAVLE-h264
- 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used d
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
pud_ben
- Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)
QPSK
- 这是关于QPSK调制解调的VerilogHDL语言的代码，还有用Modelsim仿真的工程文件。testbench都已经写好了。-This is the QPSK modulation and demodulation of VerilogHDL language code, as well as with Modelsim simulation project file. testbench have been written.
verilog_code_for_double_fpu
- 64位FPU，内含testbench，已经通过验证仿真。-64-bit FPU, embedded testbench, simulation has been validated.
iic
- i2c接口的功能实现代码，用VERILOG编写，并附有testbench.-i2c interface function implementation code, written in VERILOG, along with testbench
sv_lab_switch
- system verilog ASIC 验证平台编写详细实例-system verilog testbench for ASIC
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
System-verilog-Overview
- Verilog overwied. it has writing verilog testbench guidlines
sdram_5
- SDRAM的verilog描述，包含顶层设计，测试平台代码，精确描述-SDRAM is verilog descr iption, including top-level design, testbench code, an accurate descr iption of