搜索资源列表
ADC_AD7490
- THIS PROJECT IMPLEMENTED ON VITERX 4 FPGA and THE COMPLETE SOURCE FILES testbench, design file UCF file are there and THIS ADC is maily configured with SPI protocol interface SPI CLK,SPI DATA, SPI LE, the SPEED OF OPERATION OF SPI CLK is 10 MHZ
OFDM_Convolution
- 自己写的卷积码，能实现仿真结果,有testbench文件-Write your own convolution code, simulation results can be achieved
OWIRE
- OWIRE verilog代码，实现了单总线上的通信传输的HDL顶层，子模块设计和testbench内容-The code of 1wire bus
SystemVerilog
- SystemVerilog设计(第二版) 用于编写TESTBENCH；-eetop.cn_SystemVerilog for Design(Second Edition)
串并转换
- vhdl实现串并转换，其中附有源程序和testbench程序，可以用modelsim仿真
tst_bench_top
- I2C控制总线的测试平台testbench，用于验证I2C主机冲击交互的正确性-I2C control bus test platform testbench, used to verify the correctness of the interaction I2C master impact
sdram_latest.tar
- SDRAM的控制代码，包含文档说话和testbench测试代码-SDRAM control code, including documents speak and testbench test code
LEDWATER
- 跑马灯/流水灯代码，实现左右移和幂布式流水四种模式的循环变换，并包含testbench文件。-Marquee/water lamp code, move around to achieve the water and power distributed four modes of loop transformations, and includes testbench files.
uart
- Atmega 328 UART clone with testbench, cannot be synthesized to gates
Spread-Spectrum-Analyzer
- Spread-Spectrum-Analyzer in verilog with testbench
ImageProcessor-(1)
- a testbench which can be used to use in imge processing. this creates pixel values depending on the threshold given. Can be used to sharpen images using FPGA
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
debouncer_vhdl
- RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
RGB2YUV_TB
- 将RGB颜色空间转换为YUV颜色空间的testbench，用verilog写得，可以测试看看。-Convert RGB color space to YUV color space testbench, written in verilog, can test and see.
abs_mode
- abs_mode 2-complement souce and testbench code
dct_parallel.tar
- paralel DCT hardware in verilog with testbench
trafficlight
- VHDL实现红绿灯，multisim测试通过，可直接烧录到FPGA板上进行测试,带testbench-VHDL realize traffic lights, multisim tested, can be burned directly to the FPGA board for testing, with testbench
fft_small_tb
- vhdl testbench for 8pt fft
Counter3
- 基于Xilinx 的ISE 14.7 的计数器程序，包含testbench文件和约束文件-Based on the Xilinx ISE 14.7 Counter program, including testbench and constraints files
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench