搜索资源列表
M_UartRecv0_tb
- rs232串口基于VHDL的testbench代码 很有用的 经过验正的 -RS232 serial port based on testbench s VHDL code is very useful to the RS232 serial port based on testbench VHDL code is very useful to pass the test
Writing_Testbench
- Writing_Testbench 一本介绍testbench非常好的一本英文书籍。-Writing Testbench a very good testbench describes an English book.
Uart-Verilog
- verilog实现串口通讯，包括verilog代码和testbench代码-verilog serial communication, including the verilog code and testbench Code
filter_tb
- 滤波器的testbench，测试模块，自带输入输出-Filter testbench, test module, comes with input and output
FIR
- This is verilog code for FIR Filter with testbench availble.
mearly
- 一个简单的检测101序列的米利型状态机，里面包括了testbench的源代码。-Millie state machine with a simple detection of 101 sequences, which includes the testbench source code.
moore
- 一个简单的检测101序列的摩尔型状态机，里面包括了testbench的源代码。-A simple detection of 101 sequences of the mole state machine, which includes the testbench source code.
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
fpu_double
- The Verilog version of the code is in folder “fpu_double”, and the VHDL version is in folder “double_fpu”. There is a readme file in each folder, and a testbench file to simulate each core. These cores are designed to meet the IEEE 754 standard f
spi
- It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.-It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.
3-ddc-cic_5hb_firmatlab-testbench)
- 三通道上下变频cic_5hb_firmatlab仿真程序-Three-channel down conversion cic hb fir matlab simulation program
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]
gen_tb
- 自己写的perl程序，可以根据逻辑代码的top文件自动生成verilog的testbench，方便做simulation，提高效率-perl program,written by myself, can automatically generate verilog testbench according to the logic of the code top file, easy to do simulation, improve efficiency
cp_model
- 原创协处理模型，异步并行接口，verilog实现，可作为仿真testbench用 -Co-processing model, asynchronous parallel interface, verilog achieve, can be used as a simulation testbench
class09_A
- Verilog 状态机编写按键消抖，并且testbench-Verilog write key debounce
64Bit-Look-Ahead-Adder-Verilog-Code-with-Testbenc
- 64Bit Look Ahead Adder Verilog Code with Testbench
fullAdder_4bit
- This is fullAdder_4bit with testbench.
uart2bus_latest
- uart IP, including rx,tx module,and FSM control,data paser logic. including: testbench-uart IP
convolution
- 卷积 严格遵守时序的一维卷积运算，用testbench测试了-convolution write a VHDL file to compute one-dimensional convolution latency 14
VHDL-Code-and-TestBench-Code
- 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector