搜索资源列表
scrambler
- Verilog编写的ADC加扰程序（scrambler）里边附有加扰器的说明，实验可以把数据打散，可自行写testbench测试-Verilog prepared by the ADC scrambled program (scrambler) inside with scrambler descr iption, experimental data can be broken up, write their own testbench test
i2c_testbench
- i2c verilog rtl with testbench very good code and works perfectly with cadence ius and ncverilog
16_sd_test
- sd卡的测试工程 sd卡的测试工程 sd卡的测试工程-sd card testbench
fpga
- 有关FPGA的好多资料的综合汇总，包括夏宇闻-Verilog经典教程，Verilog-testbench的写法，Altera+FPGA／CPLD设计高级篇，Altera+FPGA／CPLD设计基础篇等好几本书，超值-A comprehensive summary of a lot of information about FPGA, including Xia Wen-Verilog classic tutorial, Verilog-testbench writing, senior Alte
2D-DCTVERILOG
- 2D DCT VERILOG CODE WITH TESTBENCH WHICH HAVING 1D DCT TRANSPOSE MATRIX
firfilterPfpga
- FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
DDS
- 利用ISE中的ip核产生正弦和余弦波形，包含有test测试文件-ISE ip core cosine sine testbench
Parallel_LDPC_Sim
- 并行LDPC的测试工程，包括编解码，和双码字之间的能量泄露比例；-testbench for parallel ldpc codec
code_test
- uvm testbench 例子，可以在questa软件里运行，运用shell脚本，在cygwin环境中执行，非常方便-Uvm testbench example, you can run in questa software, the use of shell scr ipt, in cygwin environment, very convenient
tunjiu
- IDW inverse distance weighting method, The signal spectral analysis and filtering, This program has exceeded the performance of other algorithms.
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
sdram
- sdram的控制程序，以及相关的testbench(sdram control module)
seq
- 实现序列检测功能，新手编程，已经在modelsim里检验过了功能完整，内附模块化testbench(Sequence detection function, novice programming)
eetop.cn_UVM
- UVM 的 入门实例，一个完整的能够跑通的实例。其中包括DUT代码，Testbench代码，(UVM entry example, a complete example of running through. These include the DUT code, the Testbench code,)
New folder
- clock div testbench design and frquency division
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
apb_uart
- 带apb接口的uart,带testbench，测试过，可以使用(The uart module with apb interface)
multiplier_TB
- multiplier testbench
adder_sub_TB
- adder/subtractor testbench
simulation
- 7segment testbench and velilog