搜索资源列表
simulation2
- 7segment ctrl testbench and velilog
anc dec
- encoder,decoder,testbench and run files
test
- 滤波，实现图像的滤波功能的testbench文件，可以适当参考(Filter filtering, testbench file to achieve image filtering function, you can properly refer to)
uygulama1
- verilog hdl, haladder testbench
pwm with tb final
- pwm with testbench in verilog ,synthesizable
mycode
- 这是open silicon interlaken user interface的一个driver,采用的是uvm的架构，能够实现single/dual/quad segment的配置(This is a open silicon Interlaken user interface driver, using the UVM architecture, to achieve the configuration of single/dual/quad segment)
uart
- 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
Clock_Synchronization_Module
- 数字接收机中频部分数字时钟的设计 包括matlab仿真 verilog代码、 testbench代码 以及word设计文档(Design of medium frequency digital clock in digital receiver Including Matlab simulation Verilog, testbench code, and design documents)
FFT_Module
- 接收机数字部分FFT模块的代码 包括verilog代码、 matlab仿真、 word文档 testbench 实现FFT(The code of the digital part FFT module of the receiver Including Verilog, matlab simulation, testbench Implementation of FFT)
Orthogonization_Module
- 接收机数字部分正交混频模块‘ 包括verilog代码 matlab仿真 word文档 testbench代码(Receiver digital part orthogonal frequency mixing module ' Including Verilog code Matlab simulation Testbench code)
CIC_Filter_Module
- 数字接收机cic抽取模块 抽取倍数可以选择 包括verilog代码 word文档 matlab仿真 testbench代码(CIC decimation module of digital receiver Extraction multiple can be selected Including Verilog code Word document Matlab simulation Testbench code)
ezidebug-code
- Ezidebug 支持Xilinx，chipscope 寄存器链插入、数据采集和导出、重建testbench和软件仿真验证(Ezidebug supports Xilinx, chipscope register chain insertion, data acquisition and export, reconstruction of testbench and software simulation verification)
verilog
- 8位计数器，可以实现计数器的相关功能，内涵verilog文件和testbench文件(8 bits counter,include v and testbech files ,has the ability of 8 bits counter)
float_adder
- 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
1
- Hi This is an example of file ZIP Best regards
cy7c443
- 存储器仿真模型，建立testBench，可对cyc443存储器进行功能仿真。(TestBench memory, can establish simulation model, function simulation of cyc443 memory.)
verilog add4
- 分两部分，基于verilog的四位和八位加法器设计，用synopsys的VCS仿真工具进行功能仿真，掌握基本的makefile编写以及linux操作。(Divided into two parts, four and eight adder based on verilog design, function simulation with synopsys VCS simulation tools, master the basic makefile writing and Linux.)
fifo_test
- fifo IP测试工程，有完整的testbench 直接编译仿真即可(FIFO IP test project, completed testbench .direct compilation and simulation)
vhdl_testbench_tutorial
- This file learns how to write testbench in vhdl