搜索资源列表
frequency divider and testbench
- a frequency divider and test bench with simulation results
sel
- fpga i/o 速率测试代码,含有testbench(FPGA i/o rate test code, containing testbench)
aes-master
- Verilog写的AES加密解密代码,带testbench。(AES encryption code written by Verilog with testbench.)
AHB RAM
- Verilog写的 AHB总线接口的SRAM代码,带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
apb_uart_sv-pulpinov1
- SystemVerilog 写的APB总线接口的uart 代码,带testbench.(Uart code of APB bus interface written by SystemVerilog, with testbench.)
electrical lock
- 一个用Verilog写的电子锁工程,带testbench。(An electronic lock project written in Verilog with testbench.)
ModelSim电子系统分析及仿真
- 此文档详细说明了如何利用Modelsim软件对FPGA逻辑代码进行功能仿真和时序仿真的方法,并通过相关例子进行讲解说明(This document explains in detail how to use Modelsim software to perform functional simulation and time series simulation of FPGA logic code, and explain how to use some examples.)
FP_adder
- 32 bit floating point adder with testbench
HDL_equation
- Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop
adder
- 实现了加法器功能,包含testbench(Implements the adder function)
31条CPUtest
- CPU testbar 关于31条CPU的测试数据(CPU test 31 cmd CPU testbench & testdata)
uart_rx
- Verilog实现的RS232发送和接收程序,有完成的verilog代码,testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)
uvm实战源码
- uvm实战教程源码,丰富的uvm demo testbench,可以学习uvm各个阶段的testbench搭建技巧,能学习到大量的uvm testbench搭建技能,比如factory和寄存器模型等重要机制,非常值得学习
ethernet_ip_verilog
- 以太网的ip,用verilog写的,包含testbench,用于FPGA以太网设计参考
NCO VHDL IMPLEMENTATION
- its NCO vhdl implementation very useful and helpfull for beginners. it has vhdl files and testbench. wish you best of luck.
W25Q80NE verilog Model
- SPI FLASH官方仿真模型方便modelsim testbench调试仿真(Official simulation model facilitates debugging and simulation)
通用异步收发器
- 用Verilog编写的uart通用异步收发器带testbench
2D的DCT变换
- 二维DCT变换,附源码以及testbench,以及相应的数学知识
Lpfilter_20190503
- 环路滤波器是通信信号调制解调中最重要的一个部分,环路滤波器设计的好坏将直接影响到接收机的性能指标,二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源,是现代通信中非常实用的技术,本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块,并包含了完整的testbench模块,对于初学者非常有用。(Loop filter is the most important part of communication signal modulation a
SPI接口Verilog实现
- 里面有主机发送模块和从机接收模块。主机发送32位16进制数(一位一位发送),工作在模式0。压缩文件内代码可直接运行,另附上testbench文件可以进行modelsim仿真。此代码根据论坛里一位大哥的代码改编,后来找不到是谁了。。。使用状态机编写主机的发送模块,由于项目仅仅需要主机发送所以从机的接收模块没有写成32位的,但是代码风格清晰,可以直接修改,复写率极高且非常好理解!