搜索资源列表
verilog--maopao-paixu
- 用verilog实现的冒泡排序法 ，有testbench-Implemented using verilog bubble sort, there is testbench
mp3decoder
- verilog实现mp3解码程序，包括testbench-mp3 decoder verilog implementation procedures, including the testbench
Am29lv160d
- 在逻辑的系统仿真中使用的FLASH模型（AMD的Am29lv160d），包括VHDL代码文件和verilog代码文件和testbench，并且有相应的pdf说明文档。-In the logic system used in FLASH simulation model (AMD s Am29lv160d), including VHDL and Verilog source code files of documents and testbench, and the corresponding
spi_verilog
- SPI协议Verilog HDL程序，内含testbench 文件
Chapter6-9
- 第六章到第九章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
ads1278
- AD1278的接口程序，Verilog的。包含TESTBENCH，仿真通过。尚未在硬件上调试。-the interface between fpga and ad1278,contain testbench.
counter60
- Verilog语言编写的模60计数器和testbench-Verilog language model 60 counters and testbench
MinWinsockSpi
- verilog ADPLL file with testbench
VCchuankou
- verilog ADPLL file with testbench
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
risc
- 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
custom_cordic
- verilog编程开发的cordic例程，计算SIN,COS功能与计算幅值角度功能可设定，运算宽度可设定，并有完善的TESTBENCH。-Verilog programming developed CORDIC routines to calculate SIN, COS function and calculating the amplitude of the perspective of function can be set, computing the width can be set,
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
register
- it is source code of 32 bit register and testbench for tht register written in verilog.
rom_table
- rom vector table vhdl and Testbench
Memory
- Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
asynfifo
- 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
fir
- 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
canbus
- 用verilog编写实现的CAN总线控制器源码，自带testbench，解压后用ISE打开工程文件即可。-Prepared with the verilog source code to achieve the CAN bus controller, bring their own testbench, after decompression project file can be opened with the ISE.