搜索资源列表
i2c_slave
- Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)
I2C_slaver_verison3.0
- I2C从机模块，包含testbench，平台是vivado,仿真测试通过。(I2C slave module, including testbench, the platform is vivado, simulation test passed.)
New folder
- clock div testbench design and frquency division
SEQ_DETECTOR
- 这是一个四位串行数据检测器，一共有三种模式可以选择：递增（检测连续四位递增序列），递减（检测连续四位递减序列）和不变（检测连续四位不变序列）。整个设计采用同步时钟，异步复位，用米利状态机，并配置好了仿真环境和仿真文件。(This is a four bit sequence detector, including three modes that can be selected: increment mode (detecting four consistency increment data)
anc dec
- encoder,decoder,testbench and run files
uygulama1
- verilog hdl, haladder testbench
uart
- 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
ADC_Data_Recv_Module
- 接收机测试输入信号， 生成正余弦波，采样率、频率、幅度、相位可调节 并将生成的数据进行输出 压缩包包括Verilog代码、testbench代码、word文档 matlab仿真代码(The receiver tests the input signal, Generation of positive cosine wave, sampling rate, frequency, amplitude, phase can be adjusted And output the generated da
float_adder
- 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
frequency divider and testbench
- a frequency divider and test bench with simulation results
aes-master
- Verilog写的AES加密解密代码，带testbench。(AES encryption code written by Verilog with testbench.)
electrical lock
- 一个用Verilog写的电子锁工程，带testbench。(An electronic lock project written in Verilog with testbench.)
FP_adder
- 32 bit floating point adder with testbench
HDL_equation
- Verilog Program to implement the function f=x+yz and Testbench for all the possible inputs using For Loop
adder
- 实现了加法器功能，包含testbench(Implements the adder function)
spi slave程序
- spi slave的verilog程序，有测试平台testbench程序，实现fpga作为salve的功能(spi slave verilog program)
uart_rx
- Verilog实现的RS232发送和接收程序，有完成的verilog代码，testbench等。(UART send and receive verilog code, including verilog source code, testbench etc.)
ethernet_ip_verilog
- 以太网的ip,用verilog写的，包含testbench,用于FPGA以太网设计参考
W25Q80NE verilog Model
- SPI FLASH官方仿真模型方便modelsim testbench调试仿真(Official simulation model facilitates debugging and simulation)
SPI接口Verilog实现
- 里面有主机发送模块和从机接收模块。主机发送32位16进制数（一位一位发送），工作在模式0。压缩文件内代码可直接运行，另附上testbench文件可以进行modelsim仿真。此代码根据论坛里一位大哥的代码改编，后来找不到是谁了。。。使用状态机编写主机的发送模块，由于项目仅仅需要主机发送所以从机的接收模块没有写成32位的，但是代码风格清晰，可以直接修改，复写率极高且非常好理解！