搜索资源列表
jsq
- 本程序为24小时计时器，稳定无误差。简单好用，是Verilog HDL语言初学者的指引。-This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.
mytime
- Verilog实现的实时时钟 功能，时分秒-Verilog timer
Timer_sigtap
- 用Verilog HDL语言写一个计时器。其实就是在计数器的时钟输入端输入一个固定频率的时钟-Verilog HDL language used to write a timer. Is actually counter clock input of a fixed frequency clock input
05_ledtimer
- 数码管显示的时钟,verilog HDL 基础教程-a timer basied on led
design-a-clk-system-by-verilogHDL
- 利用verilog语言描述的具有调时、定时、闹钟、报时等功能的时钟系统-Verilog language to describe the use of a tune, time, alarm clock, timer and other functions of the clock system
clock
- 自己用Verilog HDL编的一个时钟程序，可以自动计时，设置闹钟，倒计时等功能-a timer programed with Verilog
24stimer
- 篮球24s定时器的verilog代码，内涵代码以及程序逻辑说明-basketball 24s timer code of verilog
pit8253
- this is a code of 8253 programme interval timer in verilog
vcc
- 用verilog设计一个8位可自动重载的定时器-An 8-bit auto-reload timer designed with verilog
timer_ip_core
- timer ip core 8 bit, verilog simulation and coding
sysclk
- 在nios环境下，结合verilog语言开发，功能是验证系统的定时器功能-Nios environment, combined with the verilog language development, functional verification system timer function
traffic-light-Verilog
- 交通灯分为X组和Y组，每组包括了2位倒计时数码管和红黄绿三色LED信号灯（每组包括﹢、-两小组，显示内容一样），考虑到应用需求，要求芯片可通过I2C接口连接到上位机，以调节内部控制寄存器,此为Verilog代码，包含led、seg、timer等模块。-Traffic lights are divided into groups X and Y groups, each including two digital countdown yellow-green and red LED lights
seg7
- verilog HDL编写的FPGA定时器并用数码管显示(Verilog HDL prepared by the FPGA timer and digital display)
shiyan
- 0到59分59秒运动计时器，带有复位开始暂停按键功能(0 to 59 minutes and 59 seconds of motion timer with reset pause button start function)
miaobiao7
- 秒表计数（verilog）可以实现百分秒，秒，分的计数60进制，可以暂停，复位(Stopwatch count (Verilog) can achieve 100 seconds, seconds, the count is 60 hexadecimal, you can pause, reset)
timer0
- 一个简单的timer，包括定时器，计数器功能模式，非常实用，供参考(A simple timer, including timer, counter function mode, very practical, for reference.)
module clock
- 一款运动计时器的设计，包含了时、分、秒的设计。(The design of a sports timer includes hour, minute and second designs.)
counter
- 基于fpga的倒计时器。 可实现6位数的倒计时，通过按键设置初始值，倒计时结束提醒等功能(An inverted timer based on FPGA)
24_Timer
- 使用Verilog编写的24位定时器，具有apb 总线接口，可以设置工作方式和计数初值。(The 24-bit timer written by Verilog has APB bus interface, which can set working mode and count initial value.)
basketball_24time1
- 该文档主要是用verilog语言实现篮球24秒计时器，这是我做的数字电子技术课程的一次大作业。 里面为整个文件夹，解压之后可在Quartus13.0上直接运行。(This document mainly uses Verilog language to realize basketball 24 second timer, which is a big assignment of digital electronic technology course I do. It contains the