搜索资源列表
epcverilogTimer
- 用verilog编写的epc的仿真定时器。用quartus2 仿真-Epc prepared with verilog simulation timer. Simulation with quartus2
cshiyan2012
- 基于EDA软件平台上，用硬件描述语言verilog设计完成分频器、计数器、串行移位输出器、伪码发生器、QPSK I/Q调制器、QPSK I/Q解调器，基于选项法中频调制器，再将各个模块综合起来组成一个完整系统；并用quartusII软件对其进行仿真验证。-EDA software platform based on the hardware descr iption language verilog design complete shift of the frequency divider,
count60
- 基于de2板的数字计时器，使用verilog hdl 语言。很好的新手教程-Based on the the the de2 board digital timer, the use of verilog hdl language. Good newbie tutorial
clock_timer
- 时钟，计时器，23小时59分59秒的时钟，可自动进位计时，Verilog编写-Clock, timer, 23 hours, 59 minutes, 59 seconds of clock, automatic binary timing, Verilog prepared
digital_clock
- QUARTUS中实现数字钟，有计时计分计秒的功能，整点报时的功能，用VERILOG实现。-QUARTUS achieve digital clock, a timer function scoring the seconds, the whole point timekeeping function, using VERILOG implementation.
8253
- 8253可编程定时器/计数器芯片 VeriLog实现-8253 programmable timer/counter chip VeriLog achieve
quartus_works_first
- 基于verilog语言的，FPGA程序，实现可暂停的计时器与数码管显示功能，计时范围0~99秒，精度0.01秒，在EP1C3T100C8上亲测通过-Based verilog language, FPGA program implementation can pause the timer with digital display function, time range from 0 to 99 seconds, precision 0.01 seconds, measured by the
24
- 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
lan
- 基于Verilog的篮球计时器，可以实现正常篮球比赛所需的各种功能-Basketball timer
univ_TIMER
- verilog source code of programable timer
uart_server
- 24路串口转1路串口服务程序, 包括FIFO模块，串口接收，发送模块，定时器模块，检测控制模块等。采用Verilog编写-24 way serial ports to 1 serial port, including FIFO module,RX module,TX module, timer module, detection and control module, etc.. Verilog preparation
time
- Verilog语言编写的，利用分频定时器的方法在数码管上显示0-59 按秒显示。-Verilog language, the method of the dividing timer is displayed on the digital display 0-59 seconds.
StopWatch
- verilog实现数字式秒表，秒表有一个按键开关：当电路处于“初始”状态时，第一次按键，计时开始（“计时”状态）；再 次按键。计时停止（“停止”状态）；第三次按键，计时器复位为 0’0’.0’’，且电路恢复到“初始”状态。详见压缩文件包内pdf说明。-Verilog in implementing digital stopwatch, stopwatches have a key switch: when the circuit is in the initial State, firs
clock
- 原创数字钟verilog程序，能实现数字钟基本功能，如：计数，跑表，定时，闹钟。用于ISE软件。-Original digital clock verilog procedures, to achieve the basic functions of digital clock, such as: counting, stopwatch, timer, alarm clock.
SDRAM_interface
- SDRAM verilog 代码，已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a re
Timing-
- 利用verilog设计的停车场中的计数器计时器和计费器，完成智能管理效果-Use the counter timer and meter parking lot in the Verilog design, intelligent management
DW_apb_timer
- verilog实现计时器timer，可直接用于芯片开发中。-verilog achieve timer, it can be directly used for chip development.
dw_apb_timers_db
- verilog实现timer参考文档，可用于实现timer。-verilog achieve timer reference documentation can be used to implement the timer.
FND timerk (2)
- fnd timer fpga verilog
071162程序
- 设计一个用于篮球比赛的定时器。要求： （1）定时时间为24秒，按递减方式计时，每隔1秒，定时器减1； （2）定时器的时间用两位数码管显示； （3）设置两个外部控制开关，开关K1控制定时器的直接复位/启动计时，开关K2控制定时器的暂停/连续计时；当定时器递减计时到零（即定时时间到）时，定时器保持零不变，同时发出报警信号，报警信号用一个发光二极管指示。 （4）输入时钟脉冲的频率为50MHz。 （5）用Verilog HDL语言设计，用Modelsim软件做功能仿真，用Quartus II综