搜索资源列表
uart_regs
- 串行通讯ip核，经过仿真验证，综合，可以参考使用-Serial communication ip nuclear, through simulation, synthesis, can refer to the use of
15Altera_IP
- 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN
com_to_TCPIP
- 串口转TCP/IP 实用程序 可以把串口数据通过TCP／IP协议在网络上传送-Serial transfer TCP/IP utilities
RS232_NIOS_Verilog
- 5个文件，包含了RS232的nios实现和Verilog实现方式。其中,RS232的nios核实现只需要按照文件描述可以轻松实现^_^，个人比较推荐！RS232的Verilog实现需要编程，例程方便使用。RS232正在进一步学习中，有兴趣的可以探讨。-the realizition of rs232 interface by niosii uart ip core of Altera.it seems a most conveniet way.
exp
- 《arm9嵌入式系统开发与实践》光盘资料，包括uart,DMA,IIC,GPRS驱动程序-" Arm9 embedded system development and practice of" CD-ROM, including the uart, DMA, IIC, GPRS driver
UART_REF
- 使用VHDL语言编写的UART IP code, 有完整的SIMULATION-uart IP code with vhdl
jtag_uart
- SOPC jtag uart 系统集成编译的IP核-Jtag-uart IP core in SOPC
UART
- design IP UART by Verilog, VHDL-design IP UART by Verilog, VHDL...
uart
- vistual dsp++下的uart驱动（用fpgaUART的IP）-vistual dsp++ the uart driver (with fpgaUART the IP)
uart_latest.tar
- VERILOG串口IP核，在XC2S200E测试过-UART IP CORE
man2uart_latest.tar
- fpga uart串口ip核，源代码例程。-fpga uart ip core
SimpleWiFi-uart--WiFi
- Simple WiFi无线透传模块是一款高性能、高性价比的单面邮票孔式嵌入式WiFi模块产品。SimpleWiFi最大的特点是配置简单、启动速度快，最快启动速度小于1秒。Simple WiFi是基于Uart与Spi接口的符合WiFi无线网络标准的嵌入式模块，内置无线网络协议IEEE802.11协议栈以及TCP/IP协议栈，能够实现 用户嵌入式设备数据到无线网络之间的转换。通过Simple WiFi模块，传统的嵌入式设备也能轻松接入无线WiFi网络。 - SimpleWiFi is a
UARTWISHBONECompatible---Downloads
- 16550 uart code lattice cpld fpga 已经验证-16550 uart ip core
uart_io_test
- uart io test,是可用的uart ip,可综合，可用FPGA实现，能直接用于产品-uart io test, is available uart ip, can be integrated, the available FPGA, can be directly used for product
UART-to-Bus-Core-Specifications
- The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. This core can be used during initial board debugging or as a permanent solution when high speed interfaces are not required. The i
uart2bus_latest
- uart IP, including rx,tx module,and FSM control,data paser logic. including: testbench-uart IP
IP
- USB+UART+I2C+VGA+ARM7+MC8051 altera IP核-USB+UART+I2C+VGA+ARM7+MC8051 Verrlog VHDL
uart_test
- altra fpga nios 开发uart工程-UART IP and test on nios
TX_IP_Source
- 串口发送ip核，配合 nios 使用，减少资源开支。(uart transmit TX_IP_Source)
uart_latest.tar
- UART的VHDL建模代码，是一个标准的IP核(UART's VHDL modeling code is a standard IP core)