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uart_tx_rx
- 该工程用verilog编写,已通过串口调试助手调试通过,接收模块采用8倍波特率采样数据,有较好的滤波功能,在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complet
keyboard
- 这是Verilog开发键盘控制程序的入门实例,内容详尽,包括工程所需的所有类型文件,可在开发板上直接运行。-This is a Verilog development of the keyboard entry control procedures instance, detailed, including the engineering required for all types of files can be run directly in the development board.
wishbone_i2c_master
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ:44425312 QQ群:50585234(群名称:FPGA4u) gtalk:fpgaforu@gmail.com 网站:www.fpga4u.com 淘宝网店:http://shop34914329.taobao.com/ 我们以一个计
iic.cx
- 本帖最后由 NovaCao 于 1-18-2009 18:02 编辑 使用Quartus II进行仿真 QQ:44425312 QQ群:50585234(群名称:FPGA4u) gtalk:fpgaforu@gmail.com 网站:www.fpga4u.com 淘宝网店:http://shop34914329.taobao.com/ 我们以一个计
calculator
- 课设一个,又臭又长,是一个用verilog编写的计算器,对应革新科技的某个sopc开发平台,键盘会扫描,七段二极管会译码且是并行输出,上传的是整个工程,在该开发平台上基本正常,主程序段编写的较为幼稚,希望大家多多扔玉。注:主程序段预计做八位计算器,后来因为实验平台只有六个数码管无奈之下后两位没接,主程序中的ac有问题,在开发平台上没效果,压缩包里的图是主程序在quartus下的仿真图,开发环境是quartus,不知应选哪项。最后:初次上传欢迎指正 -Set up a class, but als
Bin2Grey
- 一个用Verilog语言实现的二进制码到BCD码的一种转换方法的实现。包含工程文件和实现文档。-Verilog language implementation with a binary code to BCD code conversion method as a realization. And the achievement of the document contains the project file.
multipler3
- 一个用Verilog语言实现的三位二进制选举法。包含工程文件和实现文档。-One with the Verilog language implementation of the three binary electoral law. And the achievement of the document contains the project file.
compare8
- 一个用Verilog语言实现的八位二进制数比较器。包含工程文件和实现文档。-One with the Verilog language implementation of the eight binary comparator. And the achievement of the document contains the project file.
led7
- 一个用Verilog语言实现的七段数码管显示。包含工程文件和实现文档。-One with the Verilog language implementation of the seven-segment LED display. And the achievement of the document contains the project file.
ClockRun
- 一个用Verilog语言实现的简单的时钟模拟。包含工程文件和实现文档。-Verilog language implementation with a simple analog clock. And the achievement of the document contains the project file.
counters
- 一个用Verilog语言实现的变计数器。包含工程文件和实现文档。-Verilog language implementation with a variable counter. And the achievement of the document contains the project file.
fir_memory
- 用memory编写的verilog代码,可用于工程应用,已经过仿真-Verilog code written with the memory can be used for engineering applications, has been simulation
paobiao
- 基于Verilog HDL的完整数字跑表工程,在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙,秒,分。 有开始,暂停,复位功能。 学习VerilogHDL的经典例子,添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
synchronousSerialDataTransfer
- 周立功教科书上的同步串行传输verilog.hdl程序源码及工程文件,是用quartus ||综合过的了-synchronous serial data transfer
nios_lcd_3c120
- Cyclone III FPGA Nios II LCD开发程序,包括QuartusII工程及Verilog源码。-Cyclone III FPGA Nios II LCD development process, including the QuartusII engineering and source code.
Work_with_Modelsim_SE_and_Quartus_II
- 仔细讲解了如何在Modelsim中建立Altera的仿真库(Verilog HDL),如何使用Modelsim建立工程以及代码调试中的注意事项。-Carefully explained how to create Altera simulation Modelsim library, how to use Modelsim to establish engineering and debugging the code in the note.
PS2andRS232
- 基于Verilog语言PS2接口和RS232接口的实现 有文档说明,工程实例.可用来学习Verilog语言.-Based on Verilog Language PS2 interface and RS232 interface implementation are documented, project examples. Can be used to learn the Verilog language.
I2C_ise9migration
- IIC 的Verilog实现,工程是在Xilinx的ISE9.1上实现的-IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1
pos
- POS(10GE)verilog代码,加入到工程中就成为仿真平台POS发包、接收器。-POS(10GE)receiver and sender
clock_generator
- 基于FPGA的时间转换器的一个ISE工程,使用verilog语音-Converter based on FPGA time a ISE project, use the verilog voice