搜索资源列表
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核,该CPU具有32位数据宽度,5级流水线结构和指令预判和中断处理功能,适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
cordic
- 用verilog实现的一个基于流水线结构的正余弦信号发生器,六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
SRC
- 流水线cpu 顶层模块verilog源代码,和ALU子模块源代码-Pipelined cpu top-level module verilog source code, and the ALU sub-module source code
PipelineCPU2
- Modulsim下Verilog写的五级流水线32位简易CPU-five level pipeline CPU written in Verilog.
My_RASrm
- 流水线处理器的Verilog代码,结构简单,基本功能-the pipeline processor,code in Verilog
DataCycle
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-cpu cpu cpu cpu cpu cpu cpu cpu
PipelineSim
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PIPELINE
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
PipelineCPU
- 一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
april2010_1
- 基于FPGA的方向滤波指纹图像增强算法实现,本文利用FPGA具有丰富寄存器资源、可满足高速系统设计等特点,设计了一种基于FPGA纯硬件方式实现方向滤波的指纹图像增强算法。设计采用寄存器传输级(RTL)硬件描述语言(Verilog HDL),利用时分复用和流水线处理等技术,完成了方向滤波指纹图像增强算法在FPGA上的实现。-Directional filtering fingerprint image enhancement algorithm based on FPGA using the FP
PipelineSim
- 用verilog编写的简单流水线CPU,指令集根据DLX指令集修改而来。只支持定点操作.-Verilog prepared by the simple lines with a CPU, instruction set modified from under the DLX instruction set. Supports only fixed-point operation.
multiplier_interface
- verilog 写的工程,是个基于流水线的乘法器-verilog write the works, is based on a pipelined multiplier
pipelined_computer
- 基于de2-board的汇编以及verilog的五段流水线CPU代码,适合新手学习-Based on the de2-board assembler, and the five-stage pipelined CPU verilog code, suitable for novice learning
cordic
- verilog实现的cordic算法,经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
src
- 自己写的一个求两个32位操作数的最大公约数处理器的verilog代码,采用的是流水线结构-A seek the greatest common divisor of two 32-bit operands processor verilog code pipeline structure
code
- 32bits流水线加法器,verilog语言的,xilinx公司芯片上运行通过-The 32bits pipelined adder verilog language, xilinx chip run through
pipeline
- 一个流水线设计提高FPGA运行主频的实例-a pipeline demo for FPGA written with verilog
CPU
- 流水线简单CPU设计,基于简单的数字系统设计,为verilog语言,电路设计基于基本的数字电路-Pipelined CPU design, design of digital system based on a simple, Verilog language, based on the basic digital circuit design
pipline
- 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
mea_word
- 自己编的处理器verilog源码,实现了8位处理器的功能,包含流水线-mcu verilog