搜索资源列表
zhuangtaiji
- 基于FPGA的用状态机的verilog程序源代码-FPGA-based state machines using verilog source code
verilogiic1121
- 一个基于verilog的iic协议的控制器，用状态机结构编写，可以将数据写入eeprom中，再读出来。-A protocol based on verilog for iic controller state machine structure with writing, data can be written to the eeprom, reading them out.
zhuangtaiji
- 状态机实现，通过简单的程序实现状态机，让你最快的掌握用VERIlog语言写的状态机-State machine implementation, through a simple procedure to implement state machines, allowing you the fastest master the language used to write state machine VERIlog
drink_mashine
- 用verilog语言实现自动售货机功能，其中使用了状态机来实现。-Vending machine using verilog language function, which uses a state machine.
state_verilog
- 用VERILOG实现状态机，对状态机的理解很有帮助-Use VERILOG implementation state machine, the understanding of the state machine is very helpful
led_flow
- verilog 控制灯的闪烁，运用状态机写的-this code is about the Flicker of light
led_state3
- verilog 三段式LED,有益于参考学习状态机！-verilog led three state
bitdetect
- verilog代码编写110100序列的序列检测器，用状态机实现，包括仿真测试代码-verilog coding sequence detector 110100 sequence state machine implementation, including simulation test code
vga_pannel_design
- verilog代码写的控制vga显示的实例，利用状态机进行描述，很好的参考例子-verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer
zhuangtai
- Verilog语言实现状态机的设计，实现的状态机总共有三种，均给出了具体的实现方案-Design and implementation of the state machine of the Verilog language, the state machine to achieve a total of three, were given a concrete implementation scheme
fsm
- verilog四状态状态机 带异步清零端和测试向量 mealy型状态机 很好用哦 -verilog four state machine with asynchronous clear end and test vectors mealy-type state machine oh well
FSM
- 用verilog语言编写的状态机，包括状态机的各种标准写法，包括了modelsim的整个工程。-This code is used to describe the FSM. And it includes all modes of it.
black_jack
- verilog编写的21点游戏，用状态机写的，A可以表示1也可以表示11.-verilog 21-point game, written by a state machine
shop
- 自动售货机 Verilog 语言 状态机 FPGA 源代码 论文完整程序及验证结果-Vending machines FPGA Verilog language source code for the state papers and verify the results of a complete program
New_UART_verilog
- 这个是最新的UART的verilog代码，里边含有和UART相关的所有function,比如状态机，接收发送FIFO等相关代码。-New UART verilog sample code,Include FIFO code state mashine code ,recevier/trasmiter code
washmachine
- 基于FPGA的洗衣机控制器 verilog语言 实现注水 脱水，正反转反复控制 状态机-FPGA-based controller verilog language washer water dehydration, reversing repeated control state machine
hengwenxiang
- 恒温控制器，由状态机连接到温度传感器，温度控制的控制。该代码是用verilog编写的恒温控制，在每个语句有一个中文的描述-Thermostat controller, controlled by a state machine connected to the temperature sensors, temperature control. The code is written in verilog thermostat control, after each statement has a
traffic
- 基于Verilog的交通灯，包含分频器模块、计数模块以及控制模块。状态机编写-Verilog-based traffic lights, including the divider block, counting module and a control module. Write state machine
state
- fpga verilog入门经典系列完整版，下载即用:简单状态机-fpga verilog simple state
zhuangtaiji
- 状态机 多种状态的转换 verilog语言编写-Convert verilog language write state machine multiple states