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sdram_mdl
- 用Verilog HDL编写的SDRAM控制程序，在DE2-70上测试通过，有很大的参考价值。-SDRAM control program written using Verilog HDL DE2-70 test passes, great reference value.
sdram_mdl
- SDRAM VERILOG源代码 控制读写-SDRAM VERILOG source code control read and write
Altera-SDRAM_controller-IP-CORE
- ALTRA官方提供的SDRAM的控制内核，VHDL和VERILOG版本都有，希望对大家有用-The ALTRA official SDRAM control kernel, VHDL and VERILOG version have the hope that useful
my_test_rw_pack9
- 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclon
MICRON_2048Mb_ddr2
- micron ddr2 sdram verilog model and documents
SDR-SDRAMverilog
- 经典三星SDR SDRAM读写verilog代码分享-Classic Samsung SDR SDRAM read and write verilog code share
Sdram_Control_4Port
- SDRAM控制器的verilog源代码实现-SDRAM controller Verilog source code to achieve
Sdram_PLL
- SDRAM的锁存器控制程序verilog代码-The SDRAM latches control program verilog code
Sdram_RD_FIFO
- 用SDRAM实现的读堆栈的verilog源代码-Read stack implemented SDRAM Verilog source code
Sdram_WR_FIFO
- 用SDRAM实现的写堆栈操作的verilog源代码-SDRAM write stack operations Verilog source code
sdram_mdl
- 基于verilog的SDRAM读写控制,源自特权同学-SDRAM controller use to read or write base on verilog，it is from teqian
ddr2_v5
- 基于FPGA v5的ddr2-sdram控制器的设计verilog-Based on FPGA v5 of ddr2-sdram controller design verilog
SDRAM50M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是50M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 50 m, the hope can help you
SDRAM100M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是100M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 100m, the hope can help you
SDRAM_verilog
- SDR SDRAM用verilog语言实现-SDR SDRAM using verilog language
DDR3-SDRAM-Verilog-Model(1)
- contains the information and codes of DDR3 memory model
Sdram_Control_8Port
- 用verilog写的8端口SDRAM模块-8-port SDRAM module
61EDA_C915
- altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
verilogsram
- 一个基于verilog的sdram读写控制器，可以将数据写入sdram并读回。-One based on the sdram verilog write controller, data can be written to and read back sdram.
sdram_latest.tar
- sdram 控制器 verilog 源码-verilog source of sdram control