搜索资源列表
sdram_verilog
- 基于verilog语言的SDRAM控制器-SDRAM controller based on verilog language
sdram_module3
- 能够实现16位的SDRAM的读写，没有仿真文件，只有SDRAM读写的源代码，用Verilog编写-can complete read or write sdram， only include Verilog code and no simulation files
sdram_ov7670_rgb
- ov7670+sdram+vga显示的代码，用verilog写的 ，fpga开发时的参考资料-code ov7670+sdram+vga displayed with verilog written references when fpga development
SDRAM_Test
- SDRAM Verilog HDL 测试代码，含有时序约束。-SDRAM Verilog HDL test code contains timing constraints.
Sdram_Control_4Port
- verilog 编写的sdram控制代码，很好的参考例子-sdram verilog write control code, a good reference example
SDRAM_0
- verilog写的sdram控制测试程序，测试成功了，可以直接在飓风2上跑-sdram verilog write control testing procedures, the test is successful, you can run directly on the Hurricanes 2
MICRON_2048Mb_ddr2
- MICRON DDR2 SDRAM芯片Verilog仿真模型以及器件编号说明
SDRAMverilog
- SDRAM verilog 串口实例 带有RTL图 及详细的注释-SDRAM verilog RTL serial examples with diagrams and detailed notes
SDRAM_96M_UART_TestOK
- SDRAM_96M_串口实验OK 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-SDRAM_96M_ serial experiments OK a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
DACtoADCtoSPI_Triangle1
- DACtoADCtoSPI_Triangle1.zip 一个项目工程，硬件包含Altera FPGA，SDRAM，串口，使用verilog-DACtoADCtoSPI_Triangle1.zip a project engineering, hardware contains Altera FPGA, SDRAM, serial port, using verilog
sdr_sdram_EP1C3T144C8N
- 基于FPGA芯片 EP1C3T144C8N的SDRAM verilog hdl代码-the SDRAM verilog hdl code based on FPGA chip-- EP1C3T144C8N
SDRAM_CTRL
- SDRAM 读写的程序 用verilog 写的SDRAM的底层驱动-SDRAM literacy program
testsdram
- 一个用Verilog语言编写的SDRAM控制器源码, 逻辑清晰, 结构合理!-SDRAM controller is a source code in Verilog language, logical, reasonable structure!
verilog_sdram
- I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to
DDR3-SDRAM-Verilog-Model
- ddr3模型以及代码和测试程序，不过带有小瑕疵-ddr3 model and code and test procedures, but with small flaws
DDR2Controller
- DDR2 SDRAM Control Verilog RTL Code
wb_sdram_ctrl.tar
- Generic Wishbone R3 compliant SDRAM controller written in Verilog
mt48lc32m16a2
- SDRAM的仿真模型Verilog。用于美光mt48lc32m16a2，可在ModelSim下用。-Simulation Model of SDRAM
sdram_src
- 基于FPGA的读写控制，sdram，简单易懂，verilog代码描述-FPGA-based read and write control, sdram, easy to understand, verilog code Descr iption
SDRAM_Verilog
- 本源码由Verilog语言编写，用硬件实现SDRAM的读写和存储数据功能，包括SDRAM的控制模块、初始化模块、读写模块等！-The source the Verilog language, implemented in hardware SDRAM read and write and store data, including SDRAM control module, initialization module, reader module, etc!