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ref-ddr-sdram-verilog.zip
- sdram的verilog的源码实现
标准SDR SDRAM控制器参考设计_verilog_lattice
- 标准SDR SDRAM控制器参考设计，Lattice提供的verilog源代码-standard SDR SDRAM controller reference design, the Lattice Verilog source code
sdr sdram controller
- ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
ref-sdr-sdram-verilog
- 本代码是用VRILOG语言写的SDRAM的控制器的标准代码,供开发SARM参考.-this code is used to write the language VRILOG SDRAM controller standard code for the development of SARM reference.
very-good-ok-ref-ddr-sdram-verilog
- Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
ref-sdr-sdram-verilog
- sdram的控制器 verilog源码
sdram
- sdram controller.verilog
sdr-sdram-(verilog)
- Altera的SDR SDRAM模型，verilog实现，带说明书文件以及仿真文件、SDRAM原型文件。-Altera' s SDR SDRAM model, verilog implementation, with manual files and simulation files, SDRAM prototype file.
sdram_mdl
- verilog编写的对SDRAM的控制的源代码，开发FPGA/CPLD-verilog SDRAM write control of the source code, development FPGA/CPLD
controller-design-of-sdram-
- 基于FPGA对sdram控制器的设计（VERILOG语言）-FPGA-based controller design of sdram (VERILOG language)
sdram
- verilog sdram读写控制，实现数据存储于发送-sdram read and write，data store and communication
SDRAM
- 用Verilog写的SDRAM测试程序。先向SDRAM里面写数据，然后再将数据读出来做比较。-Written using Verilog SDRAM test program. Xianxiang SDRAM write data inside, and then read out the data for comparison.
verilog-SDRAM
- 用verilog语言写的SDRAM读写控制器的程序，经测试有效。-Written in verilog language SDRAM read and write controller procedures, the test is valid.
sdram controller
- Introduction Synchronous DRAMs have become the memory standard in many designs. They provide substantial advances in DRAM performance. They synchronously burst data at clock speeds presently up to 143MHz. They also provide hidden precharge time and t
sdram_ip
- 完成SDRAM的上电配置，状态机编写其读写模块，存储模块，并通过两个异步作为存储和读取的通道(Complete the SDRAM power-on configuration, the state machine to write its read-write module, memory module, and through two asynchronous as a storage and read the channel)
my_sdram_mdl
- 此功能为altera fpga 的sdram 控制器，串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
sdr_sdram
- sdram使用接口仿真，altera公司ip使用方法(sdram verilog. SDRAM using interface simulation, Altera company IP use method)
FPGA_SDRAM
- 基于Verilog语言的SDARAM代码(SDARAM code based on Verilog language)
sdram
- sdram的驱动开发，支持单字节读写，全页读写，自定义长度读写。(SDRAM drive development, support single byte read and write, full page read and write, custom length read and write.)
sdram_test
- 针对黑金AX309开发板的SDRAM控制程序。基于ISE 14.7，语言为Verilog。实测可用。(For the black gold AX309 development board SDRAM control program. Based on ISE 14.7, the language is Verilog. Measured available.)