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UART
- design IP UART by Verilog, VHDL-design IP UART by Verilog, VHDL...
UART
- verilog语言编写在CPLD上构建一个遵循串口通信规范的程序-verilog language serial procedures
FPGA-Uart
- fpga串口通讯程序。用Verilog语言编写-fpga serial communication program. Verilog
UART-DISPLAY
- lcd 显示，Verilog语言，串口接收数据，并在LCD中显示，波特率9600，包括主文件，LCD控制文件，波特率发生文件-lcd display Verilog language, serial port to receive data, and the LCD display, baud rate of 9600, including the master file, the LCD control file, the baud rate generator file
uart
- UART模块的verilog代码，经过测试，能够实现正常的接收和发送功能。-Verilog code for UART module has been tested, it is able to achieve normal receive and transmit functions.
uart
- uart的Verilog代码，经过测试没有问题，有测试文件-uart Verilog code, no problem tested, the test file
uart-in-verilog
- develop uart using verilog language-develop uart using verilog language...
async_transmitter
- 使用Verilog编写串口发送16bits，内含补码运算；参数化编写。-verilog uart 16bits transmitter two s complement parameter code
UART
- 本论文使用Verilog HDL 语言描述硬件功能，利用QuartusII 5.0在 FPGA 芯片上的综合描述,采用模块化设计方法设计UART（通用异步收发器）的各个模块。-The paper using Verilog HDL language to describe hardware features, the use of the FPGA chip QuartusII 5.0 comprehensive descr iption of the modular design approa
uart
- 用verilog描述的uart收发模块，比较经典。-With the the UART transceiver module Verilog described, classic.
UART
- UART --串口发送与接收verilog代码，适用于QUATUS II 开发环境下，适合verilog入门的学员-UART- on serial port ,send and receive signal, suitable for QUATUS II development environment for Verilog entry students
uart
- 利用verilog实现与uart的通信，uart接口-uart interface realize
uart-project
- uart verilog zzpoifeow fwpoep wf wpo fpw pdfikwpoe e opfewiepfow [efkpow f pkw[fpkdw[kef[w fkepowkf[ok[ew f[pekwp fpoefi[wie-UART verilog
uart-jiazhen
- 用 verilog 编写的串口通信程序，编译通过，代码完整，非常好用下载就可用，全力推荐新手使用-Using verilog prepared by the serial communication program, compile, code integrity, very easy to use you can download to use, fully recommended for newbies
UART-finite-state-machine
- 基于Verilog语言的，用有限状态机实现Uart，很实用-UART design based on finite state machine
UART
- FPGA实现串口的收发，可以改波特率。Verilog HDL语言-FPGA Verilog HDL
UART
- 串口及其测试向量程序,VERILOG 代码-Serial and test vector program
uart
- 一个实用的uart协议模块，使用verilog 实现-A practical uart protocol modules, use verilog to achieve
uart
- 用verilog写的程序实现串口通信， 用verilog写的程序实现串口通信， -the program is based on verilog, and it s fuction is comunicate with uart
clkdiv
- Verilog UART分频时钟 产生9600波特率-Verilog UART baud rate divided clock generated 9600