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uart_verilog
- Verilog HDL语言编写的uart程序，在别人基础上改动和优化完成，quartus ii 10.0编译通过，可综合，板上仿真通过。将PC机发送的字符串发送回，可一次发送多个字符串。-Verilog HDL language uart program, in others on the basis of changes and optimization is complete, quartus ii 10.0 compiler, integrated, on-board through si
uart_tx
- UART 发送端程序 verilog语言编写 9600波特率-UART transmit side program verilog language 9600 baud
uart_latest.tar
- VERILOG串口IP核，在XC2S200E测试过-UART IP CORE
uart_tx
- 硬件描述语言设计的串口发送源代码UART TX SOURCE CODE-Verilog HDL UART TX RTL SOURCE CODE
3.UART_test
- FPGA的UART通信实验，已经过验证，使用verilog程序编写。-The FPGA UART communication experiment has been verified using verilog programming.
FPGA9_VGAaUART
- 基于FPGA Verilog VGA 显示 UART 数据-Based on the FPGA Verilog VGA display UART data
uart_verilog
- UART串口通信代码，FPGA编程，用Verilog代码编写-UART serial communication code, FPGA programming with Verilog coding
Xilinx_xapp341_uart_verilog
- Xilinx应用笔记关于UART的verilog实现方法和例子说明-Xilinx application note on the UART verilog implementation methods and examples
xapp341_verilog
- Xlink应用例子关于UART的Verilog实现的源代码-Xlink application examples about UART Verilog realization of the source code
verilog_uart_valid
- 用verilog语言写uart通讯的原理以及经过验证的源码-Uart verilog language written with the principle of communication and a proven source
uart16750_latest.tar
- uart 控制器 verilog / vhdl 源代码-uart control verilog /vhdl source
uart_Verilog
- uart接口verilog源码，实现数据串并行的转换。内容包含十个代码文件。-uart Interface verilog source of data for serial-parallel conversion. Contains ten code files.
18B20
- verilog 写的18b20温度采集程序，并通过串品模块送出-verilog 18b20 uart ise
uart_fifo
- 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
fpga_49
- pci接口 spi接口 和 uart接口数据传输 sopc挂载 verilog语言编写-pci interface spi and uart interface data transfer interfaces sopc mount verilog language
URAT-code
- 使用Verilog HDL语言编写的URAT接口代码，实现串行数据传输功能-UART of Verilog HDL code to realize serial communication functio by Simon of Shenzhen University.
uart_loop
- 串口通信,采用verilog实现串口通信程序-uart,Serial communication
uart_latest.tar
- 串口（UART）的verilog源代码，可以供设计参考-Serial port (UART) of the Verilog source code, can be used for reference in design
pci_uart_parity
- uart pci 等verilog hdl 代码-uart pci such as verilog hdl code
uart2bus_latest.tar
- 这是一个用Verilog HDL和VHDL设计的UART控制器的IP核，里面有详细的源代码-This is a Verilog HDL and VHDL design UART controller IP core, which has detailed source code