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uart_io_test
- verilog中UART的PC通信协议,看过的人都说好,已经验证正确性,很不错的代码。-verilog in the PC UART communication protocols, seen people say well, has verified the accuracy, very good code.
uart_verilog
- 232串口Verilog语言实现,可供新手参考编写,不太完善,需做补充。-Uart 232 Verilog
uart_tx
- 带有奇偶校验功能的的串口发送模块,实现uart功能。verilog硬件描述语言实现-With the function of parity of serial port to send module, uart functions.Verilog hardware descr iption language to realize
rs232_des
- uart verilog code using ram and a-uart verilog code using ram and all
test232_8
- 串口调试,已经证明是好使的,使用Verilog编程,放心使用-uart
uart_tr(3)
- uart_tr 异步串口通信主机 使用verilog HDL语言编写-uart_tr the host of the uart
ISEuart
- 实现串口通信,Verilog语言,ISE开发环境,实现8字节的传输-Uart transition
uart2
- 基于Xilinx ISE的uart传输代码,使用verilog语言完成-Based on Xilinx ISE uart transmission code, completed with verilog language.
IIC_uart
- 本程序是用Verilog编写的,可实现IIC协议,同时联合串口uart通信,可实现pc机调试-The program is written in Verilog, enabling IIC protocol, while the United serial uart communications, enabling pc machine debugging
rs232
- 用Verilog语言实现了UART串行通信协议-Verilog language used to achieve a UART serial communication protocol
uart_ps2
- ps2接口的verilog module 负责用键盘发送数据,附带仿真task仿真,代码简单明了。 uart接口的verilog module ,通过PC机上的串口助手接收并显示键盘发送的数据 FPGA 板调试OK-ps2 verilog module with uart verilog module,fpga simulation ok.ps2 send data and uart get data and display in PC
VerilogUart
- UART 串口通信模块,Verilog 实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-UART serial communication module, Verilog implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
uart_rx
- a verilog code to receive data in uart standard
uartfifo
- fifo模式下的uart串口verilog的源程序-fifo mode serial uart verilog source
uartverilog
- 自动收发的verilog编写的uart串口程序-Automatically send and receive serial uart verilog written procedures
uart_control
- uart控制 串口控制 top层接口 总控制-uart contrl Verilog
txd_interface
- 串口发送接口控制联合uart_txd_contrl实现-uart TXD Verilog
txd_control
- uart串口发送控制模块 适合于485 422 232等接口-uart TXD——contrl Verilog
rxd_control
- 串口接收控制模块联合uart——rxd_interface使用-uart rxd contrl Verilog
baud_control
- uart串口波特率控制,和uart——top uart——rxd_contrl 等随模块联合使用-uart baud clk Verilog