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micro uart
- 硬件uart源程序verilog HDL,即相关文档-hardware UART Verilog HDL source, that the relevant documents
verilog for uart
- 通用异步接收器/发送器(UART)是能够编程以控制计算机到附加串行设备的接口的微芯片。详细来说,它提供给计算机RS-...还有高级的UART提供了一定数量的数据缓冲,这样计算机和串行设备数据流就可以保持同样的速度。-universal asynchronous receiver / transmitter (UART) can be programmed to control computer attached to the serial device interface microchips.
u-uart
- 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
uart-verilog-vhdl
- 拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis)
uart_core_vhdlORverilog
- 串uart的vhdl,verilog,lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)\\uart 源码 (Verilog)\\uart 源码 (VHDL)\\uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice versi
uart
- 实现简单的UART功能,在QUARTUS4.0下编译通过,采用VERILOG HDL编写.
UART
- UART 串口程序,verilog语句,很好的实现了UART的通信功能!
uart
- 用Verilog实现的串口异步通信,适用于RS232
uart
- 用verilog实现UART串口收发。状态机形式实现,波特率可调(Use verilog to achieve UART serial transceiver. State machine form, adjustable baud rate)
UART发送接收奇偶校验
- 状态机,串口收发,以及奇偶校验。 even_parity.v奇偶校验; receive_byte.v字节接收; send_byte.v字节发送(state machine,UART even_parity.v even parity; receive_byte.v receiving byte; send_byte.v sending byte)
verilog
- lcd1602 12864显示程序代码,串口传输数据代码(lcd1602 12864 code,UART code.)
apb-uart
- apb—uart模块,实现中断处理和异步收发数据并处理(APB - UART module, interrupting processing and asynchronous receiving and receiving data and processing)
uart
- 此上传文件实现的功能就是FPGA里实现从PC接收数据,然后把接收到的数据发回去。 使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
12345 keyuart
- verilog实现uart串口编程 FPGA板与PC传输数据(verilog uart processing FPGA and PC communication)
UART_FPGA
- FPGA下的UART串口通信协议及控制器设计(UART serial communication protocol and controller design under FPGA)
黑金Sparten6开发板Verilog教程V1.6
- 黑金spartan的开发板教程,包含了各类接口如spi,uart,vga的用例,以及各项存储器如flash,ddr的操作方法(spartan 6 example design)
PC2FPGA_UART_Test
- 基于 fpga 的 uart 设计 波特率 115200(UART design based on FPGA)
VerilogUart_Modelsim
- 使用Verilog编写的UART ,用Modelsim仿真工程。(use Verilog Write UART Program, Modelsim simmulate the project)
apb_uart
- 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
uart
- 电脑端发送数据与FPGA接收数据程序,uart模块,以及一部分项目里包含的其他的程序(Program for sending data from computer and receiving data by FPGA, UART module)