搜索资源列表
daima
- 32bits进位选择加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits carry select adder verilog language, xilinx chip run through
daima
- 32bits提前进位加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits advance carry adder verilog language, xilinx chip run through
code
- 32bits补码加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits complement adder verilog language, xilinx chip run through
ripplecarryadder
- ripple carry adder in verilog
add_tree
- 加法树的源代码，是乘法和除法的基础，也即数字电路的verilog基础代码，已经仿真过，完全正确-Adder tree source code, multiplication and division, digital circuit verilog code base simulation entirely correct
cla32
- verilog code for cla 32 bit adder
Carry_Select_Adder_Verilog
- 进位选择加法器，verilog实现。包含3个TB。-Carry Select Adder. Verilog fulfilled. Three testbenches included.
adder16_2
- １６位２级流水线加法器的ｖｅｒｉｌｏｇ设计-16 2 pipeline adder Verilog design
adder8_4
- 用Verilog HDL编写的8位加法器程序，加法器采用4级流水线的方式实现。-8-bit adder program written using Verilog HDL, the adder 4 pipeline.
twoBitAdder
- N-bit adder implemented in verilog
PROJECT1-20130414-20130512
- 16bit adder的verilog源代码和4bit的计数器源代码-source code for 16bit adder and 4bit counter
A-4-bit-variable-modulus-counter
- 用Verilog HDL设计一个4bit变模计数器和一个5bit二进制加法器。在4bit输入cipher的控制下，实现同步模5、模8、模10、模12及用任务调用语句实现的5bit二进制加法器，计数器具有同步清零和暂停计数的功能。主频为50MHz，要求显示频率为1Hz。-A 4-bit variable modulus counter and a 5bit of binary adder using Verilog HDL design. 4bit input under the control
UDP
- 这是用Verilog HDL编写的程序 利用UDP方法实现四位加法器-This is written in Verilog HDL programs Use UDP method four adder
addr_rtl
- 利用Verilog HDL编写程序 利用assign语句实现加法器-Use Verilog HDL to write programs Using the assign statement adder
Adder12_2-6
- This an 12 bits adder in Verilog. it adds two 6 bit nibbles parallel.-This is an 12 bits adder in Verilog. it adds two 6 bit nibbles parallel.
Adder12_3-4
- This is an 12 bits adder in Verilog. it adds three 4 bit nibbles in parallel.
Adder12_4-3
- This an 12 bits adder in Verilog. it adds four 3 bit nibbles in parallel.-This is an 12 bits adder in Verilog. it adds four 3 bit nibbles in parallel.
project3_1
- 逐次进位加法器，HDl verilog语言编写，能在DE2上运行-Successive carry adder, HDl verilog language, able to run on the DE2
jianyijiafaqi
- 采用MAX+PlusII工具编辑设计的Verilog程序设计的简易加法器。可实现10以内的加法计算-Using MAX+PlusII tools to edit the design of Verilog design of a simple adder. Can be realized within 10 addition calculation
chaoqianjinweiliuweijiafaqi
- 六位加法器（逻辑门电路实现）verilog 语言编写-6 bit Adder