搜索资源列表
SUANSHUJISUAN
- 通过verilog hdl实现加法器乘法器,除法器的设计-Achieved through verilog hdl adder multiplier, divider design
delta-sigma-DAC
- 根据FPGA的∑-Δ D/A转换器的设计与实现策略,∑-Δ DAC的内部仅由2个10位的二进制加法器,1个10位的锁存器和一个D触发器组成,用FPGA实现时只需耗费极少的逻辑资源,即使用最小的FPGA也能实现。这是∑-Δ DAC实现的verilog语言-According to the FPGA Σ-Δ D/A converter design and implementation strategies, Σ-Δ DAC' s internal only by the two 10-bit
lab7
- 利用verilog语言设计32位进位选择加法器。实现高速计算功能。-Use verilog language design 32 carry select adder. High-speed computing.
modelsimPdebussy-batch-processing
- 内容包括采用Windows批处理方式高效执行Verilog仿真验证的方法,采用Modelsim+debussy联合仿真,里面包含一个加法器实例,批处理文件,仿真指令等。-Included with Windows batch efficient implementation of Verilog simulation method, using Modelsim+debussy co-simulation, which contains an example of an adder, batch
fpaddmisc-(1)
- VERILOG CODE FOR FLOating point adder
Rashed
- simple Adder in verilog (xilinx)
half
- This is a verilog half adder code
full
- This a full adder verilog code-This is a full adder verilog code
aadd4
- verilog 描述的超前进位加法器,速度较快,可综合-lookahead adder verilog descr iption, faster, can be integrated
src
- 32位加法器,verilog HDL,初级用,-32-bit adder, verilog HDL
counter
- 采用VERIlOG HDL语言设计的一个加法器项目,简单可靠,并把其中测试平台程序加入其中-VERIlOG HDL language designed using an adder project, simple, reliable, and to join the program in which the test platform
FASwitch
- Full Adder Design in Switch level Modelling using Verilog
RCA
- ripple carry adder design using verilog
Verilog_100exaples
- Verilog的100个经典设计实例,包括交通灯的设计代码,智能时钟的设计代码,各种加法器。乘法器的设计代码-100 classic Verilog design examples, including the traffic light design code, intelligent clock design code, a variety of adder. Multiplier code
32ADD
- 32位超前进位加法器,verilog hdl代码实现,包含源程序-32 lookahead adder, verilog hdl code, including source code
carry-look-ahead-adder32
- This implements Carry look ahead adder in verilog
carry_skip_adder_verilog
- 行波加法器能对两个n位数的各位同时进行加法运算的装置,可由n个一位加法器(全加器)并联而。本程序是它的verilog实现-Line wave and instruments capable of two n-digit device you carry adder, while the n by an adder (full adder) in parallel while. This program is to achieve its verilog
claadder
- 4 Bit Carry Look Ahead Adder in Verilog.
bcdadd
- 4-Bit BCD Adder in Verilog
Lab9_adder4a
- 4位加法器的设计与实现.4位加法器框图,本实验中用Verilog语句来描述.nexy3.-With the implementation of.4 bit adder block design of 4 bit adder, the Verilog statement in this experiment to describe.Nexy3