搜索资源列表
adder8
- 8位全加器，Verilog硬件语言源代码。最基础的加法器。-8-bit carry-ripple adder， the basic adder。Achieved by verilog source code.
Float_add
- 该源码利用Verilog HDL语言成功实现了浮点数的加法运算，包括全部工程以及Verilog 源码，经验证，该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful
flow_proc
- 流水线结构是在逻辑很复杂的情况下使用，通过分栈，把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。最形象的实例就是位宽较大的加法器。此程序就是verilog的实现 -In the pipeline structure is complex logic case, through the sub-stack, the complex logic into a plurality of blocks of a relatively simple implementation
fullAdder32
- 阵列加法器,实现加法功能，快速加法的功能，verilog代码-Array adder adding function to achieve rapid addition of features, verilog code
Adder_Array
- 用verilog 实现了一个加法器阵列的计算，32位，位数可以扩展。-Verilog achieved by calculating an adder array 32, the median can be extended.
adder16.v
- 这是自己写的16bit ripple 形式的加法器的代码，用verilog写的，如果有用，fell free to download-This is to write 16bit ripple adder form of code, verilog written, if useful, fell free to download
addercs16.v
- 这是自己写的 16 bits carry select adder 的verilog的代码，如果有用fell free to download-It is 16 bits verilog write their own code to carry select adder, if a useful fell free to download
fulladder.v
- 自己写的full adder的verilog代码，请大家下载。如果有问题请评论给我-Write your own full adder verilog code, please download. If you have questions, please give me a comment
day5_fastadder
- this is an implementation of fast adder algorithm in verilog.
adder4
- 利用硬件语言FPGA Verilog语言实现4位加法器的运算-Using FPGA hardware language Verilog language implementation and operation of four adder
adder5
- 5位全加器，与4位全加器相比较对新手来说更能深刻的理解Verilog语言。-5 bit full adder, compared with a 4 bit full adder for the novice can be more profound understanding of Verilog language.
FA
- 使用VERILOG實現全加器的設計,並附上TB供測試-Use VERILOG achieve full adder design, together with a test for TB
add_10
- FPGA中基于Verilog语言的10位加法器设计，适合初学者学习FPGA-FPGA Verilog language-based 10-bit adder design, suitable for beginners to learn FPGA
count15
- 用verilog语言实现15进制加法计数器的功能-Achieve 15 binary adder counter function using verilog language
halfadder.v.tar
- Verilog Code for Half Adder Circuit with testbench code-Verilog Code for Half Adder Circuit with testbench code...
fulladder.tar
- Verilog Code for Full Adder circuit with Testbench file-Verilog Code for Full Adder circuit with Testbench file...
half_sub
- 用Verilog语言实现的半加器功能，非常好的例程。-Verilog language implementation with half adder function, very good routine.
ISEadder
- 利用Verilog语言，基于ISE，设计加法器-ISE adder
codes
- 5 simple verilog codes: Arithmetic.v - arithmetic operations on verilog Accumulator.v - 8 bit adder accumulator counterfpga.v - 4 bit up counter w/ fpga code UpDown3.v - 4 bit Up-down counter w/fpga code pattefier.v - pattern/sequence ident
Accumulator
- An 8-bit Accumulator with an adder module in Verilog HDL. You can change the bus width decoding the adder.