搜索资源列表
crc7_4
- 使用Verilog HDL语言按标准编写的CRC(7,4)循环码,对学习编码有很好的指导作用!-Verilog HDL CRC(7,4) coding
byte_crc
- 字节型CRC校验 采用verilog语言设计-Byte CRC checksum type design using Verilog language
example
- FPGA大量实例,仅供参考,适合新手学习-FPGA a large number of examples for reference only, suitable for novices to learn
PCK_CRC16_D8
- VERILOG的CRC代码,节约资源,高效.欢迎提意见-good verilog for crc,is good for fpga.welcome to down
CRC16_D8_m
- 用verilog实现的crc校验,符合标准-Crc check with verilog implementation, the standard
jjm
- 用Verilog实现的crc16编码器,可以实现任意长度帧的发送信息的crc无失真编码-Implemented with Verilog crc16 encoder can send frames of any length lossless coding of information crc
cookbook
- 用于verilog入门的小程序,包括各种crc,compare等常用硬件电路的描述-verilog cookbook,including several verilog code of crc,compare circuit etc.
crc_gen.pl
- CRC verilog 生成脚本,可自己设定CRC 参数-CRC verilog generate scr ipts, you can set their own parameters CRC
my
- 64位数据的CRC-32校验的,Verilog实现,算法并行优化-64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm
gen_crc
- 任意位宽,任意多项式,并行CRC生成verilog代码脚本-CRC verilog gen scr ipt, for any width of data input
crc_tool
- 用c编写的自动生成并行crc处理的verilog代码的工具-Automatically generate the verilog code to parallel crc processing tools written with c
crc16-
- 本文档描述了一种CRC校验的方法,开发语言为verilog。程序自己写的,包括测试代码。欢迎参考-This document describes a CRC checksum method development language verilog. Write their own procedures, including test code. Welcome reference
CRC3
- CRC3算法 verilog 实现,循环校验,在传输数据时通过crc算法,验证数据是否传输正确-CRC3 algorithm verilog achieve, cyclic check whether the transmission data by the the crc algorithm, validation data transferred correctly
CRC16_8
- 利用ISE软件采用Verilog HDL语言编写CRC码,每时钟处理8bit数据,在输入序列后最终加上16位校验码。-Using Verilog HDL language CRC code, 8bit data processing per clock, after the final of the input sequence plus 16 checksum.
CRC_Tst
- 关于CRC的发射,以及接受的验证,用Verilog实现,包含testbench验证-About CRC launch, as well as acceptable verification, using Verilog implementation, including verification testbench
crc32
- crc-32 主要用于网络传输中的 检测,防止错误数据传输-verilog hdl
verilog_crc
- verilog硬件描述语言进行数据传输过程中的CRC校正。-verilog hardware descr iption language for data transmission during CRC correction.
CRC32_II
- 基于第二类LFSR串行CRC生成器的32位并行实现结构。用于SATA 3。 verilog语言。-32bit parrallel CRC module as specified in SATA 3. The module is realized with verilog.
CRC_test
- 基于verilog编写的CRC校验程序,采用LFSR电路实现。-CRC verilog
CRC32_D8
- 循环冗余校验编码,CRC32,verilog实现,xilinx平台上验证,结果可用。-CRC coding, CRC32, verilog implementation, verification on xilinx platform, the results are available.