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wddc_module
- 数字下变频的Verilog程序，测试可以直接使用，将A/D信号下变频为基带I，Q两路信号-Digital down conversion of the Verilog program, testing can be used directly to A/D signal down-conversion to baseband I, Q signals two
DMA_8237A
- 经典DMA控制器8237A的VHDL设计，对设计DMA控制器有很高的参考价值。-Classic DMA controller 8237A of the VHDL design, the design of the DMA controller has a high reference value.
UART_DMA
- 基于ALTERA公司的NIOSII的串口通信DMA传输设计-NIOSII based on ALTERA s DMA transfer of the serial communication design
usb-blaster
- quartus多种USB-bletera 自制下载线！
hdl
- cnt_top,It is used to realize a D flip flop. it is written with verilog.
Can_be_integrated_Verilog_syntax
- 可综合的Verilog语法（剑桥大学，影印）, 语法全面，适合学习或研发人员参考-Can be integrated Verilog syntax (Cambridge, photocopying), grammar comprehensive reference for learning or R & D personnel
jitter_eliminate
- verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-verilog descr iption of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted
mpeg2_idct_hw
- 2-D的DCT/IDCT在軟硬體上的verilog code-dct/idct source code for soc
MIPS1CYCLE
- MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers. b. Add the X and Y registers an
dflipflop
- d flipflop for verilog code
01chufaqi
- 带同步清0、同步置1 的D 触发器 verilog语言描述的-0 with synchronous clear, synchronous set 1 D flip-flop verilog language descr iption
DFF
- actel fpga D触发器 verilog描述-pdf actel fpga d
ass1_2_hamming
- Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a
D_chufaqi
- 用Verilog语言写一个D触发器。在时钟上升沿触发和在时钟下降沿触发。-Using Verilog to make a trigger or flip-flop.
ADC1
- 关于A/D的模拟到数字的转换，通过大家熟悉的Verilog语言实现。-On the A/D conversion of analog to digital by the familiar Verilog language.
d_chufa
- d类触发器的verilog编程及仿真，对于初学者很有用途。包括仿真实验，源代码。-d type flip-flop verilog programming and simulation, useful to use for beginners. Including simulation, source code.
1_d_ff_bottom_top
- D flip flop,由verilog 以bottom_top 形式構成的IP電路模組 -the verilog of D flip flop bottom_top architecture
2_d_ff_top_dowm
- D flip flop,由verilog 以top down形式構成的IP電路模組 -D flip flop by verilog top down
dtrigger
- 常用触发器——D触发器的VERILOG语言描述，可用Quartus II 9.0 和modelsim环境实现。-Common triggers- D flip-flop of VERILOG language descr iption available Quartus II 9.0 and modelsim environment to achieve
password
- verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。-verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the