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streamline_div
- 一个资源很省的乘法器,代码为Verilog代码,8位除法器，除法结果在8个时钟后输出.代码也可自行扩展到更大位宽.-A resource is the province of the multiplier, code for Verilog code, 8-bit divider, division results in eight clock output. Code can also extend themselves to greater width.
FPGA__source-code__Verilog
- FPGA部分基础功能源代码，适合初学者进行学习仿真，代码可读性强，通俗易懂，逻辑清晰。包括触发器，全加器，分频，并串转换，计数器，序列发生器等Verilog语言源代码。- Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Includ
clk_generator
- 时钟分频的verilog代码，能够实现小数分频，文件为Xilinx ISE工程文件-Frequency clock divider verilog codes, it is possible to achieve fractional file to Xilinx ISE Project Files
Divide
- This a divider verilog code
4.5fenpingqi
- 基于FPGA的关于verilog语言的4.5分频器及其仿真波形图-FPGA based on verilog language frequency divider and its simulation waveform in figure 4.5
N-jifenpin
- 用verilog编写的N倍奇分频源码，大家可以参考一下哈哈哈。希望大神指正-With verilog written N times odd divider source code, you can refer to Ha ha ha. Great God hope corrected
UD_DIVDER
- 定制化分频器的verilog源代码，分频器变量已参数化，好用-Customized divider verilog source code, variable frequency divider parameterized, easy to use
divider1-(3)
- Code for divider is written in Verilog where divider and dividend both are of 8 bits. Division is done using continuous subtraction method until the divisor becomes greater or equal to dividend.
chufaqi
- 这是一个用Verilog编写的一个除法器，可以快速的进行除法运算-This is a a divider, written in Verilog division operation can be quickly
fenpin
- 实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)
uart_rxd
- 用Verilog实现UART，有分频模块，可调整波特率(UART with Verilog, there are frequency divider module, can adjust the baud rate)
devider10
- 实现对时钟信号的二分频和十分频，二者作为系统的两个输出(Realization of two frequency division and ten frequency division of clock signal,and the two are used as the two output of the system.)
jiaotongdeng_fuza
- 本文基于FPGA技术的发展和Quartus II开发平台，实现路口交通灯控制器是一种解决方案。使用Verilog HDL硬件描述语言来描述语言程序的分频器模块，控制模块，数据解析模块，显示译码模块和段选位选模块，五个模块，并通过各个模块程序之间的端口合理连接和协调，成功设计出交通信号灯控制电路。在Quartus II环境下模拟，生成顶层文件下载后，在FPGA EP2C5Q208器件进行验证。(Based on the development of FPGA technology and the