搜索资源列表
div
- 实现了不恢复余数除法器，采用Verilog HDL编码，仿真通过。-Not to restore the balance achieved divider, using Verilog HDL coding, simulation through.
clkdiv
- 占空比可调 分频系数 都可随意设定的分频器，语言为Verilog HDL-Duty cycle factor can be freely adjustable frequency divider set the language for the Verilog HDL
fdivision
- 基于verilog的分频器,以及相应的test bench-A frequency divider based on verilog
Binarydivider
- 采用verilog编写的二进制分频器,常用于频率变化场合-Binary frequency divider using verilog prepared, commonly used in the frequency occasions
dividerwithsignal
- 本程序是用verilog实现带符号的二进制除法器。本代码可用。-to realize the divider
div32
- 基于verilog的分频器 23分频器 可更具需要修改成任意偶数分频器-23 divider verilog-based crossover can be even more need to modify the divider into any
verilog_std_div
- Verilog HDL语言实现任意整数分频.只需调节分频数和分频位宽即可。-Verilog HDL language to any integer divider. Simply adjust the number and frequency can be frequency division-bit wide.
div_5
- 一种技术分频器的设计，5分频为例，Verilog源码-A technology Divider, 5-band case, Verilog source code
11
- 本题为verilog HDL实现的占空比为1：1的分频器-Divider
2011-03-09
- 基于quartus II cycloneII verilog分频器-Divider based on quartus II cycloneII verilog
speaker_divider
- FPGA上蜂鸣器的驱动及测试程序,Verilog HDL语言-The divider and test program of the speaker on FPGA, in Verilog HDL language.
int_div0
- verilog编写的任意分频器，经过测试好用，准确-divider verilog any written, tested easy to use, accurate
verilog_n_evendivider
- verilog 中很好的n倍奇数分频器，开发环境为ISE10.1，仿真环境为modesim6.3-n times in good verilog odd divider, the development environment for ISE10.1, simulation environment for the modesim6.3
chufaqi
- 除法器程序，采用Verilog语言编写，并在CPLD开发板上经过验证，正确无误，希望对大家有用-Divider procedure for the Verilog language, and CPLD development board verified and correct, we hope to be useful
decimal_divison
- 使用双模计数器实现的FPGA小数分频器，语言verilog HDL。-FPGA implementation using dual-mode fractional divider counter, language verilog HDL.
zuhe
- 这个是12位的除法器，进过验证的，verilog程序，应用组合逻辑，欢迎下载-This is 12-bit divider, been to verification, verilog, application logic combinations are welcome to download
freqdivider
- Frequency divider application for Verilog programming
verilog_Common_arithmetic
- 常用逻辑运算，加法器，乘法器及除法器的verilog语言，可用modelsim或Quartus II 9.0环境-Common logic operation, adder, multiplier and divider verilog language, can be used modelsim or Quartus II 9.0 environment
DIV_5
- 该源码包包含一个奇分频分频器的Verilog代码及其测试代码。奇分频在许多分频电路中都会用到。-The source code package contains a surprising frequency divider in Verilog code and test code. Odd number of points in the frequency divider circuit will be used in.
combinational_divider
- 参数可配置的除法器verilog源代码，验证通过-verilog soure code for divider with configurable parameters